Abstract: A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.

Abstract: A method for expedited tunnel establishment with a non-Third Generation Partnership Project (3GPP) interworking gateway to access a 3GPP network is provided. A User Equipment (UE) initiates establishment of an Internet Protocol secure (IPsec) tunnel with a first non-3GPP interworking gateway associated with the 3GPP network. The UE probes availability of a second non-3GPP interworking gateway associated with the 3GPP network before the IPsec tunnel with the first non-3GPP interworking gateway is established successfully. The UE initiates establishment of an IPsec tunnel with the second non-3GPP interworking gateway in response to failing to establish the IPsec tunnel with the first non-3GPP interworking gateway and the second non-3GPP interworking gateway being available. The UE accesses the 3GPP network over the IPsec tunnel with the second non-3GPP interworking gateway.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: Provided is an electromagnetic wave reflectarray, including a first substrate, a second substrate, first wires and second wires respectively arranged on the first substrate and the second substrate along a first direction and a second direction, antenna electrodes and tuning electrodes respectively arranged into first electrode strings and second electrode strings electrically connected to the first wires and the second wires on the first substrate and the second substrate along the first direction, and a liquid crystal layer disposed between the first substrate and the second substrate. The tuning electrodes completely cover the orthographic projections of the antenna electrodes on the second substrate.

Abstract: A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.

Abstract: A semiconductor structure includes a contact plug on a source/drain region of a transistor, and a via on the contact plug. The via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward. The semiconductor structure further includes a metal line on the via.

Abstract: A hardware accelerator is provided. The hardware accelerator includes a first memory; a source address generation unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a destination address generation unit coupled to the data dispersion unit; an address queue coupled to the destination address generation unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform anyone or any combination of tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation or tensorflow space-to-depth permutation.

Abstract: A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.

Abstract: Conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: An electronic device is provided. The electronic device includes an inductor and a dielectric layer. The inductor includes a first magnetic layer, a conductive trace over the first magnetic layer, and a second magnetic layer over the conductive trace. The dielectric layer includes a first portion between the second magnetic layer and an inclined surface of the first magnetic layer. A substantially constant distance between the second magnetic layer and the inclined surface of the first magnetic layer is defined by the dielectric layer.

Abstract: A method for collecting error status information of a mobile device is disclosed. The method comprises activating an status report program; capturing a screenshot of the electronic device; receiving input text from an user interface of the status report program; and transmitting the screenshot and the input text to a server provider by the status report program.