Patents by Inventor YUAN-CHUN LUO

YUAN-CHUN LUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12200942
    Abstract: A method of writing data to a Ferroelectric-FET (FeFET) based non-volatile memory device can be provided by applying a voltage pulse at a write voltage level with a write polarity at a gate electrode of a FeFET device with reference to a source electrode of the FeFET device, as a write operation to the FeFET device to establish a state for the FeFET device, changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity, at the gate electrode with reference to the source electrode for a delay time to reduce neutralization of a trap state associated with the write operation of the FeFET device, and changing the voltage pulse, after the delay time, to a read voltage level as a read operation to the FeFET device to determine the state of the FeFET device established during the write operation.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: January 14, 2025
    Assignee: Georgia Tech Research Corporation
    Inventors: Asif Khan, Winston Chern, Yuan-Chun Luo, Nujhat Tasneem, Zheng Wang, Shimeng Yu
  • Publication number: 20230189530
    Abstract: A method of writing data to a Ferroelectric-FET (FeFET) based non-volatile memory device can be provided by applying a voltage pulse at a write voltage level with a write polarity at a gate electrode of a FeFET device with reference to a source electrode of the FeFET device, as a write operation to the FeFET device to establish a state for the FeFET device, changing the voltage pulse, directly after the write operation, to a non-zero bias voltage level with a bias polarity that is opposite to the write polarity, at the gate electrode with reference to the source electrode for a delay time to reduce neutralization of a trap state associated with the write operation of the FeFET device, and changing the voltage pulse, after the delay time, to a read voltage level as a read operation to the FeFET device to determine the state of the FeFET device established during the write operation.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 15, 2023
    Inventors: ASIF KHAN, WINSTON CHERN, YUAN-CHUN LUO, NUJHAT TASNEEM, ZHENG WANG, SHIMENG YU