Abstract: A first electronic device indicates at least two second electronic devices to enable respective sound recording functions, and indicates a third electronic device to send an ultrasonic signal. After enabling the sound recording functions, the at least two second electronic devices determine a relative location relationship between each of the at least two second electronic devices and the third electronic device based on respectively detected ultrasonic signals, and then send the relative location relationship between each of the at least two second electronic devices and the third electronic device to the first electronic device. Finally, the first electronic device sends the relative location relationship between each of the at least two second electronic devices and the third electronic device to the at least two second electronic devices and the third electronic device.

Abstract: The present disclosure relates to a digital currency-based payment method, platform and system, and a terminal, and relates to the technical field of computers. An implementation of the method includes: receiving a target payment request for a first digital currency in a frozen state, the first digital currency in the frozen state being generated based on a pre-payment request and a pre-configured pre-payment deposit smart contract; generating a second digital currency according to a target payment amount indicated by the target payment request, the first digital currency, and a pre-configured pre-payment verification smart contract; and sending the second digital currency to a first account corresponding to the first digital currency. The implementation improves the transaction security, and is conducive to protecting the rights and interests of a user.

Abstract: A ranging method and apparatus are provided. The method includes: obtaining first measurement information and second measurement information (S410), where the first measurement information includes a plurality of groups of sampled data that are obtained by a first device by sampling retroreflection measurement signals received through a plurality of antenna channels of a single antenna, and the second measurement information includes a plurality of groups of sampled data that are obtained by a second device by sampling measurement signals received through a plurality of antenna channels of each of a plurality of antennas; and determining a distance between the first device and the second device based on the first measurement information and the second measurement information (S420). In this method, ranging is performed based on multi-antenna switching frequency hopping, so that a ranging delay meets a requirement, and ranging precision and robustness are improved.

Abstract: Immersion cooling systems, apparatus, and related methods for cooling electronic computing platforms and/or associated electronic components are disclosed herein. An example apparatus includes a first chamber including a first coolant disposed therein, the first coolant having a first boiling point. The example apparatus further includes a second chamber disposed in the first chamber, the second chamber to receive an electronic component therein. The second chamber includes a second coolant having a second boiling point different that the first boiling point. The second chamber is to separate the electronic component and the second coolant from the first coolant.

Abstract: The present disclosure provides an efficient vibration reduction and isolation base supported by a chained panel fluid bladder, including a chained panel, the vibration reduction fluid bladder, vertical limiting devices and a bottom plate. The chained panel is a discontinuous structure formed by connecting chained substructure panels in series by panel hinge devices. The vibration reduction fluid bladder and the vertical limiting devices are fixedly installed between the chained panel and the bottom plate. The chained panel is constructed based on the impedance mismatch principle and provided with a mechanical device. Mechanical vibration energy is dissipated twice by the chained panel and the vibration reduction fluid bladder, thereby greatly reducing influences of mechanical device operation on a hull structure.

Abstract: The present application provides display substrates and their manufacturing methods, and display devices. A display substrate includes a base substrate, an encapsulation layer, a filter layer and optical film layers. The encapsulation layer is located on the base substrate. The filter layer is located in the encapsulation layer. The filter layer includes black matrixes. The black matrixes include black matrix openings. The optical film layers are located on a side of the encapsulation layer away from the base substrate. The optical film layers are configured to transmit part of incident light and absorb part of the incident light. A light transmittance of the optical film layers is larger than that of the black matrixes. The optical film layers include optical film layer openings. Projections of the optical film layer openings on the base substrate are located within projections of the black matrix openings on the base substrate.

Abstract: Disclosed are a method and system for evaluating sonar self-noise at a ship design stage. The method includes: building a ship structure full-scale geometric simulation model; acquiring loss factors and sonar transducer space outfitting acoustic absorption coefficient material parameters; acquiring mechanical excitation, hydrodynamic excitation, and propeller excitation; inputting the loss factors and the sonar transducer space outfitting acoustic absorption coefficient material parameters into an established statistical energy evaluation model, and applying a mechanical excitation to a face plate of foundation of the built ship structure full-scale geometric simulation model, applying a hydrodynamic excitation to the surface of a ship hull, and applying a propeller excitation to a stern shaft to perform calculation of sonar self-noise of a ship to obtain total spectral density level of the sonar self-noise; and evaluating spectral density level calculation results by index requirements.

Abstract: Disclosed are a method and system for evaluating sonar self-noise at a ship design stage. The method includes: building a ship structure full-scale geometric simulation model; acquiring loss factors and sonar transducer space outfitting acoustic absorption coefficient material parameters; acquiring mechanical excitation, hydrodynamic excitation, and propeller excitation; inputting the loss factors and the sonar transducer space outfitting acoustic absorption coefficient material parameters into an established statistical energy evaluation model, and applying a mechanical excitation to a face plate of foundation of the built ship structure full-scale geometric simulation model, applying a hydrodynamic excitation to the surface of a ship hull, and applying a propeller excitation to a stern shaft to perform calculation of sonar self-noise of a ship to obtain total spectral density level of the sonar self-noise; and evaluating spectral density level calculation results by index requirements.

Abstract: The present disclosure provides an efficient vibration reduction and isolation base supported by a chained panel fluid bladder, including a chained panel, the vibration reduction fluid bladder, vertical limiting devices and a bottom plate. The chained panel is a discontinuous structure formed by connecting chained substructure panels in series by panel hinge devices. The vibration reduction fluid bladder and the vertical limiting devices are fixedly installed between the chained panel and the bottom plate. The chained panel is constructed based on the impedance mismatch principle and provided with a mechanical device. Mechanical vibration energy is dissipated twice by the chained panel and the vibration reduction fluid bladder, thereby greatly reducing influences of mechanical device operation on a hull structure.

Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.

Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.

Abstract: Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access (DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.

Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).

Abstract: An exception stack information acquisition method, including: when a preset exception signal is sensed in a running process of a project, calling and executing an exception signal processing function to acquire first exception stack information of a native layer; reading second exception stack information recorded by an Application (APP) layer when the exception signal is sensed; and assembling the first exception stack information and the second exception stack information to obtain assembled information, then reporting the assembled information to a server, and aborting the project after reporting is completed.

Abstract: An exception stack information acquisition method, including: when a preset exception signal is sensed in a running process of a project, calling and executing an exception signal processing function to acquire first exception stack information of a native layer; reading second exception stack information recorded by an Application (APP) layer when the exception signal is sensed; and assembling the first exception stack information and the second exception stack information to obtain assembled information, then reporting the assembled information to a server, and aborting the project after reporting is completed.

Abstract: A pooling operation method for a convolutional neural network includes the following steps of: reading multiple new data in at least one current column of a pooling window; performing a first pooling operation with the new data to generate at least a current column pooling result; storing the current column pooling result in a buffer; and performing a second pooling operation with the current column pooling result and at least a preceding column pooling result stored in the buffer to generate a pooling result of the pooling window. The first pooling operation and the second pooling operation are forward max pooling operations.

Abstract: A convolution operation device includes a convolution calculation module, a memory and a buffer device. The convolution calculation module has a plurality of convolution units, and each convolution unit performs a convolution operation according to a filter and a plurality of current data, and leaves a part of the current data after the convolution operation. The buffer device is coupled to the memory and the convolution calculation module for retrieving a plurality of new data from the memory and inputting the new data to each of the convolution units. The new data are not a duplicate of the current data. A convolution operation method is also disclosed.

Abstract: A system and method for computing a sparse neural network having a plurality of output layers, each of which has a neuron value. Processing engines (PEs) each have a local memory for storing neurons for use with different weight values in a following cycle. A multiplexer selects between the input neuron or the output of the memory. Output from the multiplexor is received along with a weight input to a multiplier whose output is directed to an integrator. A decomposition technique performs a network computation through the use of intermediate neurons when the input neuron is larger than the local memory capacity, and provides data reuse by reusing neurons stored in local memory. Neural systems can be implemented using a neural index to address each of multiple PEs and a parallel-serial first-in-first-out (FIFO) to serially store values in main memory.

Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).

Abstract: A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.