Patents by Inventor Yuan-Feng CHAO

Yuan-Feng CHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor arrangement with stress control and method of making
    Patent number: 9721827
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • Cyclic epitaxial deposition and etch processes
    Patent number: 9564321
    Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Meng-Yueh Liu, Chien-Chang Su, Yuan-Feng Chao, Yuh-Da Fan
  • SEMICONDUCTOR ARRANGEMENT WITH STRESS CONTROL AND METHOD OF MAKING
    Publication number: 20150243785
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 27, 2015
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • CYCLIC EPITAXIAL DEPOSITION AND ETCH PROCESSES
    Publication number: 20140256119
    Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung TSAI, Meng-Yueh LIU, Chien-Chang SU, Yuan-Feng CHAO, Yuh-Da FAN