Patents by Inventor Yuan-Feng CHIANG
Yuan-Feng CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250029940Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: ApplicationFiled: October 1, 2024Publication date: January 23, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Publication number: 20240413115Abstract: A package structure is provided. The package structure includes an electronic component, an encapsulant, a first conductive pillar, a first dielectric layer. The electronic component has an active surface. The encapsulant encapsulates the electronic component and exposes the active surface of the electronic component. The first conductive pillar is over the active surface of the electronic component, wherein an upper surface of the first conductive pillar includes a concave portion. The first dielectric layer is over the encapsulant and the active surface of the electronic component, wherein the first dielectric layer defines an opening exposing the concave portion of the first conductive pillar.Type: ApplicationFiled: June 7, 2023Publication date: December 12, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Ling YEH, Yuan-Feng CHIANG, Chung-Hung LAI, Chin-Li KAO
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Patent number: 12107056Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: GrantFiled: January 16, 2020Date of Patent: October 1, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
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Publication number: 20240128206Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.Type: ApplicationFiled: December 5, 2023Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Peng YANG, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 11837557Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.Type: GrantFiled: November 29, 2021Date of Patent: December 5, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Peng Yang, Yuan-Feng Chiang, Po-Wei Lu
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Patent number: 11791227Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.Type: GrantFiled: May 11, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
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Publication number: 20230094668Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG
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Patent number: 11521958Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: GrantFiled: November 5, 2019Date of Patent: December 6, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang
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Publication number: 20220367304Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.Type: ApplicationFiled: May 11, 2021Publication date: November 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuoching CHENG, Yuan-Feng CHIANG, Ya Fang CHAN, Wen-Long LU, Shih-Yu WANG
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Patent number: 11428946Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.Type: GrantFiled: May 11, 2020Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
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Publication number: 20220084958Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Peng YANG, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 11189576Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.Type: GrantFiled: August 22, 2017Date of Patent: November 30, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Peng Yang, Yuan-Feng Chiang, Po-Wei Lu
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Publication number: 20210225783Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Publication number: 20210183723Abstract: A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite to the first active surface, a second semiconductor device including a second active surface and a second back surface opposite to the second active surface, a first heat conductive layer embedded in the first back surface of the first semiconductor device, a second heat conductive layer embedded in the second back surface of the second semiconductor device, and a third heat conductive layer disposed adjoining the first heat conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first heat conductive layer are in contact with the second heat conductive layer.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 11037853Abstract: A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite to the first active surface, a second semiconductor device including a second active surface and a second back surface opposite to the second active surface, a first heat conductive layer embedded in the first back surface of the first semiconductor device, a second heat conductive layer embedded in the second back surface of the second semiconductor device, and a third heat conductive layer disposed adjoining the first heat conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first heat conductive layer are in contact with the second heat conductive layer.Type: GrantFiled: December 17, 2019Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
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Publication number: 20210134781Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG
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Publication number: 20200271942Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Feng CHIANG, Tsung-Tang TSAI, Min Lung HUANG
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Patent number: 10663746Abstract: According to various embodiments, a collimator includes a substrate defining a plurality of channels through the substrate. The substrate includes a first surface and a second surface opposite the first surface. Each of the channels includes a first aperture exposed from the first surface, a second aperture between the first surface and the second surface, and a third aperture exposed from the second surface. The first aperture and the third aperture are larger than the second aperture.Type: GrantFiled: November 9, 2016Date of Patent: May 26, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Feng Chiang, Tsung-Tang Tsai, Min Lung Huang
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Patent number: 10344383Abstract: In one or more embodiments, an apparatus for processing a wafer includes a ceramic wall, a metal wall and a frame. The ceramic wall defines a chamber for accommodating the wafer. The ceramic wall has a first surface defining a first opening. The metal wall surrounds the ceramic wall. The metal wall has a second surface defining a second opening adjacent to the first opening. The frame covers the second surface.Type: GrantFiled: August 3, 2017Date of Patent: July 9, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chuan-Yung Shih, Tai-Yuan Huang, Yu-Chi Wang, Chin-Feng Wang, Sing-Syuan Shiau, Chun-Wei Shih, Shao-Ci Huang, Huang-Hsien Chang, Yuan-Feng Chiang
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Patent number: 10325854Abstract: An interposer comprises a first conductive wire having a first terminal and a second terminal, a first oxide layer, and an encapsulant. The first oxide layer covers the first conductive wire and exposes the first terminal and the second terminal of the first conductive wire. The encapsulant covers the first oxide layer and exposes the first terminal and the second terminal of the first conductive wire.Type: GrantFiled: July 18, 2017Date of Patent: June 18, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kun-Ming Chen, Yuan-Feng Chiang