Patents by Inventor Yuan-Fu Ko
Yuan-Fu Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240347382Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: ApplicationFiled: June 28, 2024Publication date: October 17, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 12057346Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: GrantFiled: September 6, 2023Date of Patent: August 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 12007435Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.Type: GrantFiled: December 8, 2020Date of Patent: June 11, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yi-Hsiu Chen, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20230420292Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: ApplicationFiled: September 6, 2023Publication date: December 28, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 11791203Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: GrantFiled: August 16, 2022Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20230050928Abstract: A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.Type: ApplicationFiled: September 10, 2021Publication date: February 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Che Huang, Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20220392798Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 11515159Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.Type: GrantFiled: December 29, 2020Date of Patent: November 29, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 11456207Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: GrantFiled: July 22, 2019Date of Patent: September 27, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20220178992Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Ching-Chih Chang, Yi-Hsiu Chen, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20210151321Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.Type: ApplicationFiled: December 29, 2020Publication date: May 20, 2021Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 10916427Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.Type: GrantFiled: July 11, 2018Date of Patent: February 9, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20200402837Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.Type: ApplicationFiled: July 22, 2019Publication date: December 24, 2020Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Publication number: 20200020576Abstract: The present invention provides a method for forming a semiconductor device, comprising: first, a target layer is provided, an etching stop layer is formed on the target layer, afterwards, a first photoresist layer is formed on the etching stop layer, and a first etching process is then performed, to forma plurality of first trenches in the etching stop layer. Next, a second photoresist layer is formed on the etching stop layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the etching stop layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the target layer.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Ching-Chih Chang, Yuan-Fu Ko, Chih-Sheng Chang
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Patent number: 10204826Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a trench in the IMD layer; performing a treatment process to transform part of the IMD layer into a damaged layer adjacent to the trench; forming a protective layer on a sidewall of the damaged layer; forming a metal layer in the trench; and removing the damaged layer to form an air gap adjacent to the protective layer.Type: GrantFiled: February 12, 2018Date of Patent: February 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Min-Shiang Hsu, Yuan-Fu Ko, Chih-Sheng Chang