Abstract: A resistive random access memory (RRAM) includes: a substrate having a first cell region and a second cell region; a fin-shaped structure extending along a first direction on the substrate across the first cell region and the second cell region; a first word line extending along a second direction on the first cell region; a source line extending along the second direction between the first cell region and the second cell region; and a single diffusion break (SDB) structure extending along the second direction directly under the source line.

Abstract: A method for operating a memory cell structure includes providing a memory cell. An erasing process is performed by applying an erasing voltage to a first gate electrode, a source region and a drain region simultaneously to attract a plurality of electrons from a substrate and to store the plurality of electrons in a first spacer and a second spacer. Afterwards, a programming process is performed by applying a pull-out voltage to the source region or the drain region to remove the plurality of electrons stored in the first spacer or the second spacer, and a read process is performed to determine whether the plurality of electrons is stored in the first spacer and stored in the second spacer.

Abstract: A bipolar junction transistor layout structure includes a first emitter including a pair of first sides and a pair of second sides, a pair of collectors disposed at the first sides of the first emitter, and a pair of bases disposed at the second sides of the first emitter. The first sides are perpendicular to the second sides. The first emitter is disposed in between the pair of collectors and in between the pair of bases.

Abstract: A bipolar junction transistor layout structure includes a first emitter including a pair of first sides and a pair of second sides, a pair of collectors disposed at the first sides of the first emitter, and a pair of bases disposed at the second sides of the first emitter. The first sides are perpendicular to the second sides. The first emitter is disposed in between the pair of collectors and in between the pair of bases.

Abstract: An antifuse one-time programmable (OTP) memory cell includes a semiconductor substrate, an isolation region, and a fin structure protruding from a top surface of the isolation region. The fin structure has an end portion with a sidewall surface above the top surface. A select gate transistor is disposed on the fin structure. The select gate transistor has a select gate traversing the fin structure, a select gate dielectric layer, a drain region, and a source region. A vertical program gate transistor is serially connected to the select gate transistor through the source region. The vertical program gate transistor has a program gate directly disposed on the isolation region and covering the sidewall surface of the end portion, and a program gate dielectric layer between the program gate and the sidewall surface.