Patents by Inventor Yuan-Hsi CHOU

Yuan-Hsi CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low loss substrate for high data rate applications
    Patent number: 10903152
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • LOW LOSS SUBSTRATE FOR HIGH DATA RATE APPLICATIONS
    Publication number: 20190214337
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Hsi CHOU, Tsun-Lung HSIEH, Chen-Chao WANG
  • Low loss substrate for high data rate applications
    Patent number: 10236240
    Abstract: In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • LOW LOSS SUBSTRATE FOR HIGH DATA RATE APPLICATIONS
    Publication number: 20170330825
    Abstract: In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Hsi CHOU, Tsun-Lung HSIEH, Chen-Chao WANG