Patents by Inventor Yuan-Hsiang Chang
Yuan-Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138737Abstract: Disclosed herein are methods for predicting the reprogramming process of cells from a microscopic image of one or more cells. According to some embodiments, the method includes capturing an image of region of interest (ROI) of every pixel of the microscopic image, followed by processing the ROI image with a trained convolutional neural network (CNN) model and a trained long short-term memory (LSTM) network so as to obtain predicted probability maps. Also disclosed herein are a storage medium and a system for executing the present methods.Type: GrantFiled: December 18, 2019Date of Patent: October 5, 2021Assignees: CHUNG YUAN CHRISTIAN UNIVERSITY, RIKENInventors: Hideo Yokota, Kuniya Abe, Ming-Dar Tsai, Slo-Li Chu, Yuan-Hsiang Chang
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Publication number: 20200126234Abstract: Disclosed herein are methods for predicting the reprogramming process of cells from a microscopic image of one or more cells. According to some embodiments, the method includes capturing an image of region of interest (ROI) of every pixel of the microscopic image, followed by processing the ROI image with a trained convolutional neural network (CNN) model and a trained long short-term memory (LSTM) network so as to obtain predicted probability maps. Also disclosed herein are a storage medium and a system for executing the present methods.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Applicants: Chung Yuan Christian University, RIKENInventors: Hideo Yokota, Kuniya Abe, Ming-Dar TSAI, Slo-Li CHU, Yuan-Hsiang CHANG
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Patent number: 10586327Abstract: Disclosed herein are methods for identifying cells undergoing reprogramming and reprogrammed cells from a fluorescence microscopic image of one or more cells. According to some embodiments, the method includes an image processing step, a cell detection step, and, optionally, a clustering step.Type: GrantFiled: February 13, 2018Date of Patent: March 10, 2020Assignees: CHUNG YUAN CHRISTIAN UNIVERSITY, RIKENInventors: Yuan-Hsiang Chang, Hideo Yokota, Kuniya Abe, Ming-Dar Tsai
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Patent number: 10423819Abstract: Disclosed herein are methods for analyzing cell kinematics in a nucleated cell culture from a time-series sequence of multiple fluorescence microscopic images of the nucleated cell culture. The method includes the steps of, (a) identifying every cell nucleus in each fluorescence microscopic image; (b) identifying every cell cluster using the cell nuclei identified in the step (a); and (c) tracking the cells and/or cell clusters using the cell nuclei and cell clusters identified for the fluorescence microscopic images in steps (a) and (b) respectively.Type: GrantFiled: October 31, 2017Date of Patent: September 24, 2019Assignee: Chung Yuan Christian UniversityInventors: Yuan-Hsiang Chang, Hideo Yokota, Kuniya Abe, Ming-Dar Tsai
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Patent number: 10332884Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.Type: GrantFiled: November 2, 2017Date of Patent: June 25, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, Jianjun Yang, Yuan-Hsiang Chang, Chih-Chien Chang, Weichang Liu, Shen-De Wang, Kok Wun Tan
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Publication number: 20190130161Abstract: Disclosed herein are methods for analyzing cell kinematics in a nucleated cell culture from a time-series sequence of multiple fluorescence microscopic images of the nucleated cell culture. The method includes the steps of, (a) identifying every cell nucleus in each fluorescence microscopic image; (b) identifying every cell cluster using the cell nuclei identified in the step (a); and (c) tracking the cells and/or cell clusters using the cell nuclei and cell clusters identified for the fluorescence microscopic images in steps (a) and (b) respectively.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: Chung Yuan Christian UniversityInventors: Yuan-Hsiang CHANG, Hideo Yokota, Kuniya Abe, Ming-Dar TSAI
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Publication number: 20190131302Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.Type: ApplicationFiled: November 2, 2017Publication date: May 2, 2019Inventors: Liang Yi, Che-Jung Hsu, Yu-Cheng Tung, JIANJUN YANG, Yuan-Hsiang Chang, Chih-Chien Chang, WEICHANG LIU, Shen-De Wang, KOK WUN TAN
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Publication number: 20180232879Abstract: Disclosed herein are methods for identifying cells undergoing reprogramming and reprogrammed cells from a fluorescence microscopic image of one or more cells. According to some embodiments, the method includes an image processing step, a cell detection step, and, optionally, a clustering step.Type: ApplicationFiled: February 13, 2018Publication date: August 16, 2018Applicants: Chung Yuan Christian University, RIKENInventors: Yuan-Hsiang CHANG, Hideo Yokota, Kuniya Abe, Ming-Dar TSAI
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Patent number: 10020385Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.Type: GrantFiled: March 19, 2014Date of Patent: July 10, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Shan Chiu, Shen-De Wang, Zhen Chen, Yuan-Hsiang Chang, Chih-Chien Chang, Jianjun Yang, Wei Ta
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Patent number: 9666680Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.Type: GrantFiled: November 18, 2015Date of Patent: May 30, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Hsiang Chang, Shen-De Wang, Chih-Chien Chang, Jianjun Yang, Aaron Chen
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Patent number: 9660106Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.Type: GrantFiled: August 18, 2014Date of Patent: May 23, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang
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Publication number: 20170141200Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: Yuan-Hsiang Chang, Shen-De Wang, Chih-Chien Chang, JIANJUN YANG, Aaron Chen
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Patent number: 9583641Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.Type: GrantFiled: December 7, 2015Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Hsiang Chang, Yi-Shan Chiu, Chih-Chien Chang, Jianjun Yang, Wen-Chuan Chang
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Publication number: 20160172200Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.Type: ApplicationFiled: December 15, 2014Publication date: June 16, 2016Inventors: WEICHANG LIU, ZHEN CHEN, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang, Chih-Chien Chang
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Publication number: 20160163722Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.Type: ApplicationFiled: January 14, 2015Publication date: June 9, 2016Inventors: Yuan-Hsiang Chang, Aaron Chen, JIANJUN YANG, Chih-Chien Chang
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Patent number: 9362125Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.Type: GrantFiled: August 7, 2014Date of Patent: June 7, 2016Assignee: United Microelectronics Corp.Inventors: Yuan-Hsiang Chang, Yi-Shan Chiu, Zhen Chen, Wei Ta, Wei-Chang Liu
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Publication number: 20160049525Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.Type: ApplicationFiled: August 18, 2014Publication date: February 18, 2016Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang
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Publication number: 20160042957Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.Type: ApplicationFiled: August 7, 2014Publication date: February 11, 2016Inventors: Yuan-Hsiang Chang, Yi-Shan Chiu, Zhen Chen, Wei Ta, Wei-Chang Liu
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Publication number: 20150270277Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Shan Chiu, Shen-De Wang, ZHEN CHEN, Yuan-Hsiang Chang, Chih-Chien Chang, JIANJUN YANG, Wei Ta
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Patent number: 8921888Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.Type: GrantFiled: March 31, 2014Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Yuan-Hsiang Chang, Sung-Bin Lin