Abstract: A hardware accelerator is provided. The hardware accelerator includes a first memory; a source address generation unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a destination address generation unit coupled to the data dispersion unit; an address queue coupled to the destination address generation unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform anyone or any combination of tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation or tensorflow space-to-depth permutation.

Abstract: A mixed-precision artificial intelligence (AI) processor and an operating method thereof are provided. The AI processor includes a first calculation module, a second calculation module and a control module. The first calculation module is configured to perform calculation based on the data with a first format. The second calculation module is configured to perform calculation based on the data with a second format different from the first format. The control module is coupled to the first calculation module and the second calculation module to select one of the first calculation module or the second calculation module to perform calculation based on an input data according to a calculation strategy.

Abstract: An artificial intelligence (AI) calculation circuit is provided. The AI calculation circuit can support various integer and floating-point calculations through the adjustment of circuit configuration. Integer multiplication and floating-point mantissa multiplication share the multiplication unit, integer comparison and floating-point comparison share the same comparison unit, integer addition and floating-point addition share the same addition unit.

Abstract: A hardware accelerator is provided. The hardware accelerator includes a first memory; a source address generation unit coupled to the first memory; a data collection unit coupled to the first memory; a first data queue coupled to the data collection unit; a data dispersion unit coupled to the first data queue; a destination address generation unit coupled to the data dispersion unit; an address queue coupled to the destination address generation unit; a second data queue coupled to the data dispersion unit; and a second memory coupled to the second data queue. The hardware accelerator can perform anyone or any combination of tensor stride, tensor reshape and tensor transpose to achieve tensorflow depth-to-space permutation or tensorflow space-to-depth permutation.

Abstract: A computing device for floating-point mathematic operation using look-up table is provided. The computing device includes: a bit arrangement unit used for receiving a floating-point input data and performing a bit arrangement or a format conversion on the floating-point input data to generate multiple index blocks; a first look-up table unit group used for receiving the index blocks and performing look-up operation using the index blocks as index to generate a plurality of look-up table results; and an operation unit used for performing operation on the look-up table results of the first look-up table unit group to generate an operation output.