Patents by Inventor Yuan-Hsiang Lung
Yuan-Hsiang Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105518Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.Type: ApplicationFiled: January 11, 2023Publication date: March 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20240030073Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: ApplicationFiled: July 19, 2023Publication date: January 25, 2024Inventors: Wei-De HO, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
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Publication number: 20230402277Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.Type: ApplicationFiled: June 12, 2022Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Patent number: 11749570Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-De Ho, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
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Publication number: 20230139799Abstract: In pattern formation method, a photomask is loaded into a lithography apparatus, an exposure light is applied to a photo resist layer formed over a substrate through or via the photomask, and the photo resist layer is developed. The photomask includes a plurality of octagonal shape patterns periodically arranged in a first direction and a second direction crossing the first direction. A width Lx of horizontal sides extending in the first direction of each of the plurality octagonal shape patterns is different from a width Ly of vertical sides extending in the second direction of each of the plurality octagonal shape patterns.Type: ApplicationFiled: March 30, 2022Publication date: May 4, 2023Inventors: Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20230067049Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is fanned in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Sheng TANG, Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Publication number: 20230062426Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Wei-De HO, Pei-Sheng TANG, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN, Chen-Jung WANG
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Publication number: 20230049896Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.Type: ApplicationFiled: April 5, 2022Publication date: February 16, 2023Inventors: Jin-Dah CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
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Patent number: 11392745Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: November 30, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 11158509Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.Type: GrantFiled: May 19, 2020Date of Patent: October 26, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
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Publication number: 20210089697Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: November 30, 2020Publication date: March 25, 2021Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10853552Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: May 6, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20200279743Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
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Patent number: 10727061Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.Type: GrantFiled: April 6, 2018Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10658184Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.Type: GrantFiled: March 30, 2017Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
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Publication number: 20190258770Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Patent number: 10282504Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.Type: GrantFiled: January 20, 2017Date of Patent: May 7, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20180233368Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.Type: ApplicationFiled: April 6, 2018Publication date: August 16, 2018Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai
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Publication number: 20180174853Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.Type: ApplicationFiled: March 30, 2017Publication date: June 21, 2018Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
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Patent number: 9941125Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.Type: GrantFiled: August 31, 2015Date of Patent: April 10, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Yang, Hua Feng Chen, Kuei-Shun Chen, Min-Yann Hsieh, Po-Hsueh Li, Shih-Chi Fu, Yuan-Hsiang Lung, Yan-Tso Tsai