Abstract: A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed bit a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Abstract: A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient.

Abstract: A multicore interface with dynamic task management capability and a task loading and offloading method thereof are provided. The method disposes a communication interface between a micro processor unit (MPU) and a digital signal processor (DSP) and dynamically manages tasks assigned by the MPU to the DSP. First, an idle processing unit of the DSP is searched, and then one of a plurality of threads of the task is assigned to the processing unit. Finally, the processing unit is activated to execute the thread. Accordingly, the communication efficiency of the multicore processor can be effectively increased while the hardware cost can be saved.

Abstract: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.

Abstract: A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient.

Abstract: A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.

Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.

Abstract: A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spread spectrum module includes a counter, a plurality of delta-sigma counters and a data shifter. These delta-sigma counters accumulate input signals, and enable a first overflow signal while accumulation of a last stage delta-sigma counter is overflowed. The frequency of the output clock can be tuned dynamically according to the first overflow signal, and the spectrum of the output clock can be spread.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.

Abstract: A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.

Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.