Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.

Abstract: An improved button actuation assembly for activating a switch on hand held devices such as portable barcode readers has an improved structure that absorbs and dissipates the force exerted on the button. The improved structure thus protects the switch and the button actuation assembly itself from being damaged by excessive force such as from an impact shock caused by dropping or misuse.

Abstract: An improved button actuation assembly for activating a switch on hand held devices such as portable barcode readers has an improved structure that absorbs and dissipates the force exerted on the button. The improved structure thus protects the switch and the button actuation assembly itself from being damaged by excessive force such as from an impact shock caused by dropping or misuse.

Abstract: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.

Abstract: A cycle time to digital converter comprises a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

Abstract: A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.

Abstract: Apparatus and methods for generating chirped return-to-zero (CRZ) differential quadrature phase-shift keyed (DQPSK) optical signals using a single modulator driven by synchronous return-to-zero (RZ) drive signals to achieve simultaneous RZ pulse formatting and chirped DQPSK data modulation.

Abstract: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.

Abstract: Optical signal-to-noise ratio (OSNR) monitoring methods and apparatus are described. A tunable optical filter filters an optical channel containing an optical signal and noise. The total signal and noise power at the output of the filter is measured as the transmittance passband of the filter is varied and the maximum and minimum powers are determined. The ratio between the maximum and minimum powers is then used to determine the OSNR of the optical channel, which, for example, can be a wavelength channel in a wavelength division multiplexing (WDM) system. The ratio of the maximum signal power to the minimum signal power and the ratio of the maximum noise power to the minimum noise power are pre-determined based on the signal modulation format type and filter passband characteristics.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: A method and apparatus for transmitting optical pulses in a dispersion-managed optical transmission system comprises determining the pulse width of optical pulses in a optical transmission channel in accordance with the path-average dispersion (PAD) experienced by that channel.

Abstract: A surface modification method of polysaccharide, the modified polysaccharide, and a method of culturing and recovery cells using the same are provided. The surface modification method of polysaccharide comprises (a) immersing a polysaccharide material in an acid, (b) immersing the polysaccharide material in an acidic solution containing a protein, and (c) immersing the polysaccharide material in an alkaline solution containing bivalent metal ions.

Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: A multipurpose memory card adapter including a base and a cover. The base has first conductive pieces corresponding to connecting fingers of memory cards of Secure Digital (SD) card, Multimedia Card (MMC) and Reduced Size Multimedia Card (RS-MMC). A plurality of guide pieces is formed at a front end of the first conductive pieces to allow for a smooth insertion of the memory cards in position. The base further includes second conductive pieces corresponding to connecting fingers of mini SD card. A first end stop at which the mini SD card to be inserted into the base arrives is located at a farther position away from an insertion opening than a second end stop for the SD card and the MMC card. A side stop and a guide chamfer are formed between the first end stop and the second end stop. Meanwhile, a detecting piece and a write protection piece are provided at one side of the base. In addition, a plurality of mounting bosses is formed at the periphery of the base.

Abstract: A slim all-in-one memory card adapter including a main body and ten contact fingers. The main body includes a slot portion at the internal side thereof and a receiving portion at the external side thereof. The slot portion includes recesses, and the receiving portion is defined by a U-shaped body formed by two side walls extending from the slot portion in such a way that the top and external sides thereof are open. A first bottom surface at a lower place and a second bottom surface at one side higher than the first bottom surface are provided between two side walls of the U-shaped body. Ten lugs are positioned on the first bottom surface. The lugs are dimensioned according to gaps of recessed edge connectors of MS (Memory Stick) series memory cards. The height h1 of the lugs is greater than the height h2 of the second bottom surface. The ten contact fingers are received within ten horizontal recesses.

Abstract: A slim five-in-one memory card adapter including a main body and different groups of contact fingers. The main body includes an internal slot and an external receptacle. The internal slot has grooves for fixing the different groups of contact fingers in place. The external receptacle is defined by a U-shaped body formed by side walls extending from the internal slot in such a way that the top and external sides thereof are open. A first side wall of the external receptacle is extended in a straight manner from the internal slot and has a height smaller than the height (t) of the MMC series memory cards while a second side wall thereof is tilted outward from the internal slot and has the same height as that of the internal slot. Meanwhile, a third side wall parallel to the first side wall is extended from the second side wall and has an equal height in comparison to that of the first side wall.

Abstract: An improved port replicator for portable electronic devices includes an angle adjustment dock which has two separated sides extended to form respectively a flange with a first bore and a connector dock located on a surface to receive transmission signals, an anchor dock having a second bore corresponding to the first bore to couple with the angle adjustment dock, and an axle running through the first bore and the second bore. The port replicator thus constructed is simple to fabricate and assemble, and is adaptable to notebook computers of varying thickness to provide a steady and secure coupling.

Abstract: A dual usage memory card connector includes a housing holding a set of terminals, the housing having two spring arms disposed at two sides and movable between a first position where a MS Duo memory card is insertable into the housing and a second position where a MS memory card is insertable into the housing, a metal top cover covering the housing, the top cover having a spring plate, a curved holding down portion forwardly extended from the spring plats for holding down a MS or MS Duo memory card inside the housing, and two limiters for holding the spring arms in the first position for the insertion of a MS Duo memory card into the housing, the spring plate being forced upwards to disengage the limiters from the spring arms upon insertion of a MS memory card.