Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Abstract: A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract: An integrated circuit includes a signal generating unit, a signal monitoring unit and a processing unit. The signal generating unit is configured to generate a control signal. The signal monitoring unit is configured to receive the control signal and accordingly output a monitor signal. The processing unit is configured to receive the monitor signal. The control signal is adjusted until the monitor signal is located within a preset range. A signal monitoring method used with the integrated circuit and a signal monitoring method used with a plurality of transistors are also provided.

Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Abstract: A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node.

Abstract: A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.

Abstract: A charge pump circuit includes a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror, a first PMOS transistor and a first NMOS switch. The first PMOS switch is coupled between the PMOS tuner and a first output PMOS transistor of the first current mirror, thus the parasitic capacitor formed between the gate and the drain of the first PMOS switch, the parasitic capacitor formed between the gate and the source of the first output PMOS transistor, and the parasitic capacitor formed between the gate and the drain of the first output PMOS transistor are equivalently coupled in series, lowering the capacitance between the PMOS tuner and the charge pump output, and reducing the clock feed through and the charge injection effect in the charge pump circuit.

Abstract: A regulating circuit is used with a buffer circuit. The buffer circuit at least includes a metal-oxide-semiconductor transistor and a voltage output terminal. The voltage output terminal is connected to a drain terminal of the metal-oxide-semiconductor transistor of the buffer circuit. The regulating circuit includes a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor. The first metal-oxide-semiconductor transistor has a source terminal and a drain terminal connected to a voltage source and a connecting node, respectively. The connecting node is electrically connected to a substrate of the metal-oxide-semiconductor transistor of the buffer circuit. The second metal-oxide-semiconductor transistor has a drain terminal and a source terminal connected to the connecting node and the voltage output terminal, respectively. A substrate of the second metal-oxide-semiconductor transistor is electrically connected to the connecting node.

Abstract: A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe.

Abstract: A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe.

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS stitch and the second MOS switch of the current source is turned on and operates in a saturation region.