Patents by Inventor Yuan-Hung Chiu
Yuan-Hung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130055Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Cheng HUANG, I-Hung CHIANG, Ji-Yuan SYU, Hsin-Han LIN, Po-Kai CHIU, Kuo-Shu KAO
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Patent number: 11735651Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.Type: GrantFiled: July 25, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
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Publication number: 20220359735Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
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Patent number: 11437498Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.Type: GrantFiled: December 7, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
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Publication number: 20210111272Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.Type: ApplicationFiled: December 7, 2020Publication date: April 15, 2021Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
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Patent number: 10861960Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.Type: GrantFiled: July 31, 2019Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Shu Wu, Ying-Ya Hsu, Ching-Yu Pan, Hsiu-Hao Tsao, An Chyi Wei, Yuan-Hung Chiu
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Patent number: 10825907Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.Type: GrantFiled: July 30, 2018Date of Patent: November 3, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
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Patent number: 10164032Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.Type: GrantFiled: December 1, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
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Publication number: 20180350927Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.Type: ApplicationFiled: July 30, 2018Publication date: December 6, 2018Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
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Patent number: 10032887Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: GrantFiled: April 17, 2017Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Publication number: 20170365674Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.Type: ApplicationFiled: December 1, 2016Publication date: December 21, 2017Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
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Publication number: 20170365691Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: ApplicationFiled: April 17, 2017Publication date: December 21, 2017Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Patent number: 9627258Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.Type: GrantFiled: June 15, 2016Date of Patent: April 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lien Huang, Li-Te Lin, Yuan-Hung Chiu, Han-Yu Lin
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Patent number: 9349831Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: GrantFiled: December 23, 2013Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Patent number: 8900960Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: GrantFiled: August 7, 2013Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Publication number: 20140106522Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: ApplicationFiled: December 23, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Patent number: 8614132Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: GrantFiled: September 22, 2011Date of Patent: December 24, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Publication number: 20130323891Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: ApplicationFiled: August 7, 2013Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chung-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Patent number: 8236659Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: GrantFiled: June 16, 2010Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
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Publication number: 20120083088Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.Type: ApplicationFiled: September 22, 2011Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hsuan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen