Patents by Inventor Yuan-Jung Kuo

Yuan-Jung Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160183153
    Abstract: The method and apparatus for switching networks are provided. The network switching method is applied to the packet switching service of user equipment (UE). The network switching method includes the steps of determining the adoption priorities of a standard switching mechanism and a non-standard switching mechanism according to decision information.
    Type: Application
    Filed: May 15, 2015
    Publication date: June 23, 2016
    Inventors: Yuan-Jung Kuo, Chi-Chen Lee
  • Patent number: 8078851
    Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: December 13, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Guan-Ying Chiou, Yuan-Jung Kuo, Hui-Chin Yang, Tzu-Min Chou, Shun-Chieh Chang, Chung-Ping Chung
  • Publication number: 20100161951
    Abstract: A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Guan-Ying Chiou, Yuan-Jung Kuo, Hui-Chin Yang, Tzu-Min Chou, Shun-Chieh Chang, Chung-Ping Chung
  • Publication number: 20100049947
    Abstract: A processor and an early-load method thereof are provided. In the early-load method, an instruction is fetched and determined in an instruction fetch stage to obtain a determination result. Whether to early-load an early-loaded data corresponding to the instruction is determined according to the determination result. A target data is fetched according to the instruction in an instruction execution stage if the early-loaded data is not loaded correctly. The early-loaded data is served as the target data if the early-loaded data is loaded correctly.
    Type: Application
    Filed: August 22, 2008
    Publication date: February 25, 2010
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Shun-Chieh Chang, Yuan-Hwa Li, Yuan-Jung Kuo, Chin-Ling Huang, Chung-Ping Chung