Abstract: An electronic includes an electronic element, an encapsulation layer surrounding the electronic element, a first circuit structure, a second circuit structure and a connecting structure. The encapsulation layer has a top surface, a bottom surface and an opening, wherein a sidewall of the opening connects the top surface and the bottom surface. The first circuit structure is disposed at the top surface of the encapsulation layer. The second circuit structure is disposed at the bottom surface of the encapsulation layer. The connecting structure is disposed in the opening, wherein the electronic element is electrically connected to the second circuit structure through the first circuit structure and the connecting structure. The connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening.

Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A risk control system for traffic devices includes a light emitting device, a processing element and a user prompting element. The processing element is electrically connected with the light emitting device, and outputs a prompt signal. The user prompting element is electrically connected with the processing element, and receives the prompt signal.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: Applications in transfusion medicine requiring platelets, and hematopoietic stem-cell transplantations require either platelets or enhancement of in vivo platelet biogenesis. Gene therapy applications of hematopoietic stem and progenitor cells (HSPCs) require effective and specific modification of HSPCs by DNA, RNA or other biological molecules. Here we disclose methods for the generation, and modification of megakaryocytic microparticles (MkMPs), proplatelets, preplatelets, platelet-like particles and megakaryocyte extracellular vesicles, that can be used in the aforementioned transfusion and transplantation medicine applications and in gene therapy applications involving hematopoietic stem cells.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A capture IR drop analyzer and an analyzing method thereof are provided. The capture IR drop analyzing method includes: receiving circuit layout information and package model information of a circuit; analyzing a plurality of circuit blocks respectively corresponding to a plurality of bump current sources according to the circuit layout information and the package model information; calculating at least one critical circuit block according to each of the bump current sources and a current demand value of each of the corresponding circuit blocks; and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: A management device comprises a first authentication module, for receiving a first information and performing a first determination on whether an administrator device is correct according to the first information; an authorization module, coupled to the first authentication module, for performing a second determination on whether the administrator device comprises an access qualification for a remote device, when the first determination is positive and when receiving a first request message for accessing the remote device; a communication module, coupled to the authorization module, for transmitting a second request message for establishing a connection with a network device to the remote device, when the second determination is positive and when determining to establish the connection with the network device; an integration module, coupled to the authorization module, for transmitting a third request message for configuring a port forwarding to the network device, when the second determination is positive.

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: An IoT gateway with configurable data transmission mode includes a data collector, a data capturer and a data uploader. The data collector is configured to collect the data provided by a data provider based on a first data policy. The data capturer is configured to capture the data collected by the data collector based on a second data policy. The data uploader is configured to handle the data captured by the data capturer based on a third data policy. The first data policy, the second data policy and the third data policy may be configured separately according to different IoT applications.

Abstract: Some implementations described herein provide a gas curtain system. The gas curtain system includes various components to prevent a gas flowing within a chamber of an interface tool from flowing through an opening into a transport carrier adjacent to the interface tool. The gas curtain system may include a gas distribution component along an edge of the opening that generates a flow of another gas across the opening towards an opposite edge of the opening. In this way, the gas from the chamber is prevented from entering the transport carrier. By preventing the gas from the chamber from entering the transport carrier, a relative humidity within an environment of the transport carrier is maintained such that condensation of moisture on one or more semiconductor wafers within the transport carrier is mitigated.