Abstract: A modeling system and modeling method based on a logical relation, including an operation task integrating module, a task interpreter, a graph layout correcting module, a graph wiring correcting module and a database model increment correcting module, wherein the database model increment correcting module includes a graph increment calculating unit and a model increment calculating unit. The system, through description of the logical relation and based on support of the automatic wiring technology, realizes the graph-model integrated generation of a new grid model of the power system which is based on the description of the logical relation; the grid model is completely defined and modified on “one net”, which is different from the original way that the power system model is established on countless net graphs, thereby helping the grid operation manager to accurately and rapidly establish and modify the grid model of the full system.

Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.

Abstract: A diaper has a diaper body, two straps and at least one strap hook-and-loop fastener. The diaper has an absorbent portion, a front covering portion connected with the absorbent portion, at least one body hook-and-loop fastener mounted on the front covering portion, and a rear covering portion connected with the absorbent portion. The straps are elongated and are respectively connected with two sides of the rear covering portion. The at least one body hook-and-loop fastener is selectively attached to the outer side of one of the straps. The at least one strap hook-and-loop fastener is mounted on one of the inner side and the outer side of one of the straps, and the at least one strap hook-and-loop fastener is selectively attached to the other strap. Therefore, the diaper can be suitable for different users of different waist sizes.

Abstract: A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.

Abstract: A method for scale adjustment of touch-based measurement equipment has steps of providing a touch-based screen with a waveform area; determining if a first-direction gesture or a second-direction gesture is present on the waveform area; when the first-direction gesture is present, determining if an object touches one of two portions of the waveform area divided along a second direction of the waveform area and incrementing or decrementing a first scale when positive; and when the second-direction gesture is present, determining if an object touches one of two portions of the waveform area divided along a first direction of the waveform area and incrementing or decrementing a second scale. Scale adjustment on touch-based measurement equipment using one finger can be implemented with the foregoing method.

Abstract: A zoom lens including a first lens group, a second lens group, and a third lens group is provided. The first lens group is disposed between an object side and an image side and has at least one aspheric surface. The second lens group has a positive refractive power and is disposed between the first lens group and the image side. The third lens group has a positive refractive power and is disposed between the second lens group and the image side. The third lens group has at least one aspheric surface. The third lens group is suitable to move relative to the second lens group for focusing.

Abstract: A zoom lens including a first lens group, a second lens group, a third lens group, and a fourth lens group with positive, negative, positive, and positive refractive powers respectively arranged in sequence from an object side to an image side is provided. The first lens group includes a first lens and a second lens. The second lens group includes a third lens, a fourth lens, and a fifth lens. The third lens group includes a sixth lens. The fourth lens group includes a seventh lens, an eighth lens, and a ninth lens. The first lens, the second lens, the third lens, the fourth lens, the fifth lens, the sixth lens, the seventh lens, the eighth lens, and the ninth lens respectively having negative, positive, negative, negative, positive, positive, positive, negative, and positive refractive powers are arranged in sequence from the object side to the image side.

Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.

Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

Abstract: A zoom lens including a first lens group, a second lens group, a third lens group, and a fourth lens group with positive, negative, positive, and positive refractive powers respectively arranged in sequence from an object side to an image side is provided. The first lens group includes a first lens and a second lens. The second lens group includes a third lens, a fourth lens, and a fifth lens. The third lens group includes a sixth lens. The fourth lens group includes a seventh lens, an eighth lens, and a ninth lens. The first lens, the second lens, the third lens, the fourth lens, the fifth lens, the sixth lens, the seventh lens, the eighth lens, and the ninth lens respectively having negative, positive, negative, negative, positive, positive, positive, negative, and positive refractive powers are arranged in sequence from the object side to the image side.

Abstract: An oscilloscope with touch control has a touch screen display unit and a waveform processing and sampling unit. The touch screen display unit is connected to the waveform processing and sampling unit and has a touch control module and a display module. The touch control module detects a touch gesture and converts the touch gesture into a set of waveform processing parameters. The waveform processing and sampling unit has at least one signal input port to receive at least one external signal to be tested, processes the signal to be tested into a corresponding waveform image, and outputs the waveform image to the display module. Accordingly, the touch screen display unit enables the operation and display of the waveform thereon and provides more space originally occupied by conventional knobs so that the display module can be enlarged or the oscilloscope can be miniaturized.

Abstract: An oscilloscope with touch control has a touch screen display unit and a waveform processing and sampling unit. The touch screen display unit is connected to the waveform processing and sampling unit and has a touch control module and a display module. The touch control module detects a touch gesture and converts the touch gesture into a set of waveform processing parameters. The waveform processing and sampling unit has at least one signal input port to receive at least one external signal to be tested, processes the signal to be tested into a corresponding waveform image, and outputs the waveform image to the display module. Accordingly, the touch screen display unit enables the operation and display of the waveform thereon and provides more space originally occupied by conventional knobs so that the display module can be enlarged or the oscilloscope can be miniaturized.

Abstract: A modeling system and modeling method based on a logical relation, including an operation task integrating module, a task interpreter, a graph layout correcting module, a graph wiring correcting module and a database model increment correcting module, wherein the database model increment correcting module includes a graph increment calculating unit and a model increment calculating unit. The system, through description of the logical relation and based on support of the automatic wiring technology, realizes the graph-model integrated generation of a new grid model of the power system which is based on the description of the logical relation; the grid model is completely defined and modified on “one net”, which is different from the original way that the power system model is established on countless net graphs, thereby helping the grid operation manager to accurately and rapidly establish and modify the grid model of the full system.

Abstract: An amplification circuit includes a first amplifier, a second amplifier, and a power supply rejection ratio (PSRR) boost circuit. The first amplifier has an output. The second amplifier has an input coupled to the output of the first amplifier and a power node coupled to a power supply line. The PSRR boost circuit is coupled between the input of the second amplifier and the power supply line, and the PSRR boost circuit comprises a resistance device and a capacitance device connected in series with the resistance device.

Abstract: The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

Abstract: A sense amplifier circuit comprises a first inverter configured to provide a first trigger point during a pre-charge stage of a READ operation of a memory cell and provide a second trigger point either lower or higher than the first trigger point during a sense stage of the READ operation of the memory cell. The sense amplifier circuit further comprises a plurality of inverters coupled between an output of the first inverter and an output of the sense amplifier and a pre-charge device. The sense amplifier circuit having a dynamic trigger point can deliver faster data access time as well as less power consumption.

Abstract: An LED lamp includes an optical part, a heat dissipation member and an electric part. The optical part includes a hollow light penetrable tube and an LED module received in the tube. The heat dissipation member is received in the tube to mount the LED module thereon. The electric part include a circuit board and a rechargeable battery arranged in the tube, and two end covers arranged at two opposite ends of the tube. The LED module is provided with at least one first LED and at least one second LED. The at least one first LED and the at least one second LED cooperatively function as a main light source to provide normal illumination when an external AC power source is supplied normally. The at least one second LED independently function as an auxiliary light source to provide emergency illumination when the external AC power source is interrupted.

Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.