Patents by Inventor Yuan-Lung Lin

Yuan-Lung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240215218
    Abstract: A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Liang LI, Chunyu WONG, John H. ZHANG, Yanzun LI, Huang LIU, Yuan Lung LIN, Haijiang YUAN, Chung-Chiang LIN
  • Patent number: 5930593
    Abstract: The present invention provides a method for forming a device on a wafer without peeling, in which the wafer has a substrate forming thereon a first dielectric layer forming thereon a first conducting layer having thereon a device area and an edge area. This method includes steps of a) forming a second dielectric layer on the device area and the edge area, b) forming a photoresist layer on the second dielectric layer, c) selectively removing the second dielectric layer, the photoresist layer, and the first conducting layer from and presenting thereby the device area and the edge area with a desired dielectric layer, and d) forming a metal film on the device area and the edge area.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: July 27, 1999
    Assignee: Mosel Vitelic Inc.
    Inventors: Cheng-Hsun Tsai, Yui-Ping Huang, Mao-Song Tseng, Yuan-Lung Lin