Abstract: A method for treating a tendon injury includes administering to a subject in need thereof a pharmaceutical composition comprising a PEDF-derived short peptide (PDSP) or a variant of the PDSP, wherein the PDSP comprises residues 93-106 of human pigmented epithelium-derived factor (PEDF), and wherein the variant of the PDSP contains serine-93, alanine-96, glutamine-98, isoleucine-103, isoleucine-104, and arginine 106 of the PDSP and contains one or more amino acid substitutions at other positions, wherein residue location numbers are based on those in the human PEDF.

Abstract: A method for treating and/or preventing osteoarthritis includes administering to a subject in need thereof a pharmaceutical composition comprising a PEDF-derived short peptide (PDSP) or a variant of the PDSP, wherein the PDSP comprises residues 93-106 of human pigmented epithelium-derived factor (PEDF), and wherein the variant of the PDSP contains serine-93, alanine-96, glutamine-98, isoleucine-103, isoleucine-104, and arginine 106 of the PDSP and contains one or more amino acid substitutions at other positions, wherein residue location numbers are based on those in the human PEDF.

Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second wall portion.

Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second wall portion.

Abstract: A manufacturing method of a trench power semiconductor device is provided. The manufacturing method includes the steps of forming a protective layer on an epitaxial layer and forming a trench gate structure in a trench formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate disposed on the shielding electrode and an inter-electrode dielectric layer disposed therebetween. The step of forming the trench gate structure includes forming an insulating layer covering an inner surface of the trench; and before the step of forming the inter-electrode dielectric layer, forming an initial spacing layer, the spacing layer including a first sidewall portion and a second sidewall portion, both of which include bottom end portions spaced apart from each other and extending portions protruding from the protective layer.

Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second side wall portion.

Abstract: A method for manufacturing a semiconductor device includes the following steps. An epitaxial layer is formed on a substrate. Then, a body is formed in an upper portion of the epitaxial layer. A first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed on the epitaxial layer. The third dielectric layer forms a second trench, and the second trench is located in the first trench. A shield layer is formed in the second trench. The upper portion of the third dielectric layer is removed, such that the upper portion of the shield layer protrudes from the third dielectric layer. A fourth dielectric layer is formed to cover the upper portion of the shield layer. A gate is formed on the third dielectric layer. A source is formed in the epitaxial layer surrounding the gate.

Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second side wall portion.

Abstract: A manufacturing method of a trench power semiconductor device is provided. The manufacturing method includes the steps of forming a protective layer on an epitaxial layer and forming a trench gate structure in a trench formed in an epitaxial layer. The trench gate structure includes a shielding electrode, a gate disposed on the shielding electrode and an inter-electrode dielectric layer disposed therebetween. The step of forming the trench gate structure includes forming an insulating layer covering an inner surface of the trench; and before the step of forming the inter-electrode dielectric layer, forming an initial spacing layer, the spacing layer including a first sidewall portion and a second sidewall portion, both of which include bottom end portions spaced apart from each other and extending portions protruding from the protective layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.

Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

Abstract: A method of manufacturing super junction device includes forming a first epitaxial layer on a semiconductor substrate. The first epitaxial layer is patterned to form a trench. The trench has a first sidewall region, a second sidewall region and a bottom region. The bottom region is positioned in between the first and second sidewall regions. A second epitaxial layer is formed on the first sidewall region, the second sidewall region and the bottom region. A portion of the second epitaxial layer on the first sidewall region and the second sidewall region is removed. An oxide layer in contact with the second epitaxial layer is formed. A gate layer in contact with the oxide layer is formed.

Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes operations below. First, an epitaxial layer is formed on a substrate. Then, a trench is formed in the epitaxial layer. Then, a first dielectric layer and a shield layer are formed in the trench, in which the shield layer is embedded within the first dielectric layer. Then, a spacer layer is formed in the trench and on the first dielectric layer. Finally, a second dielectric layer and a gate are formed in the trench and on the spacer layer, and a source is formed in the epitaxial layer surrounding the trench, in which the gate is embedded within the second dielectric layer, and the source surrounds the gate.

Abstract: A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active area, in which the termination area has the termination structure. The termination structure includes a substrate, an epitaxy layer, a dielectric layer, a conductive material layer and a conductive layer. The epitaxy layer is disposed on the substrate and has a voltage-sustaining region. The voltage-sustaining region has trenches parallel to each other. The dielectric layer is disposed in the trenches and on a portion of the epitaxy layer. The conductive material layer is disposed on the dielectric layer in the trenches. The conductive layer covers the trenches, and is in contact with the conductive material layer and a portion of the epitaxy layer, and is electrically connected between the active area and the termination area. A method for manufacturing the termination structure is also provided.

Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss.

Abstract: A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced.

Abstract: A power transistor having a top-side drain and a forming method thereof are provided. Firstly, a body layer is formed. An epitaxial layer is subsequently formed on the body layer. Then a gate trench is formed in the body layer and the epitaxial layer. Afterward, a gate structure is formed in the gate trench. Then, a doped drain layer is formed within the epitaxial layer. Next, a source is formed in contact with the body layer. Lastly, a drain is formed in contact with the dope drain layer. The structure and forming method disclosed can through arranging the drain at the top of the power transistor integrate with the newly high performance packaging design structure. Accordingly, the efficiency of the power transistor can be greatly enhanced.

Abstract: A trench power MOSFET structure and fabrication method thereof is provided. The fabrication method comprises following process. First, form an isolating trench. Then, form at least two doped regions around the isolating trench. The doped regions are adjacent and the doping concentrations of two doped regions are different. Form an isolating structure in the isolating trench. Wherein, the junction profiles of the two doped regions are made by on implantation method for moderate the electric field distribution and decreasing the conduction loss.