Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A method of refreshing a DRAM chip. A working temperature is detected for the DRAM, and a corresponding refresh interval is decided accordingly. A refresh timing clock is generated with the corresponding refresh interval, and the DRAM is refreshed. The refresh interval decreases with increased working temperature, and increased with working temperature decrease.

Abstract: The present invention relates to a method for finding the appropriate refresh interval applied for DRAM of the present invent, comprising, detecting startup, providing a clock pulse as a refresh interval, DRAM self-testing of a plurality of memory cells with the provided refresh interval, modifying the refresh interval and repeating the above steps to find the longest refresh interval as determined by the DRAM self-testing procedure, and using the determined appropriate refresh interval to refresh the DRAM. Therefore, the appropriate refresh interval, found form the method of the present invention, could be adjusted with the DRAM chip for saving the power with refresh.

Abstract: A method for generating refresh clock of a DRAM module, the DRAM module comprises a plurality of memory cells, and each memory cell comprises a storage capacitor. First, a dummy capacitor is provided, the dummy capacitor is positively correlated with the storage capacitor, and then a refresh clock is generated according to the dummy capacitor.

Abstract: An SCR-type electrostatic discharge (ESD) protection device includes a PNPN type device disposed between an input pad and ground. The device includes a P-type substrate layer into which an N-type well is formed. A first P+ layer is disposed in the N-type well, and a first N+ region is disposed within the P-type substrate layer for connection to ground. For handling positive transients, the device enters a regenerative mode by avalanching the intermediate PN junction between the N-type well and the P-type substrate layer. A forward-biased diode is provided to handle negative transients. The diode comprises a second P+ region provided in the P-sub layer to bypass the PN junction between the first N+ region and the P-type substrate layer and a second N+ region disposed in the N-type well to bypass the PN junction between the N-type well and the first P+ layer.

Abstract: A precharge circuit is operable during a standby mode to drive a word line to a low voltage level and one or more (pairs of) bit lines to a standby voltage level. The precharge circuit comprises a driver for driving the on or more bit lines to the stand by voltage level. The precharge circuit also includes a control circuit connected to a control input of the driver which control circuit receives the standby signal. The control circuit outputs a varying enable signal to the driver for varying the drive of the bit lines by the driver. The precharge circuit can include a first current limiting driver for driving the bit lines to the standby voltage level, and second driver, for driving the bit lines to the standby voltage level. The second driver has a greater switching speed, and a higher current driving capacity, than the first current limiting driver.

Abstract: In accordance with a preferred embodiment of the invention, the write cycle of an SRAM column is increased. The SRAM column includes at least one SRAM cell connected to the bit line and the bit line complement of the column. Further, a pair of select transistors are located below the bottom SRAM cell, where one select transistor is connected to the bit line and the other is connected to the bit line complement. The select transistors select whether the respective bit line and bit line complement is deselected or selected. The SRAM column further includes a pair of load transistors connected between the bottom SRAM cell and the pair of select transistors, where one of the load transistors is connected to the bit line and the other load transistor is connected to said bit line complement. In operation, since the load transistors are located below the bottom cell, there is no DC current supplied by the load transistors to flow through the entire bit line and bit line complement length.

Abstract: In accordance with a preferred embodiment of the invention, the wordline turn on voltage in an SRAM array is suppressed (e.g., maintained at or below 4.5 volts). This is accomplished by connecting a regulated voltage supply output to the wordline. The regulated voltage supply has a transfer function such that the Vccr (the output of the regulated voltage supply) does not exceed a threshold such as 4.5 volts. For example, the transfer function may be:Vccr=Vcc for Vcc<4.5 voltsVccr=4.5 volts for Vcc.gtoreq.4.5 voltswhere Vcc is the power supply voltage.As indicated above, the power consumed in an SRAM array is proportional to the selected wordline voltage. In accordance with the present invention, the power consumption will be generally unchanged when Vcc exceeds 4.5 volts.