Abstract: A chip package includes: a substrate having a first surface and a second surface; a device region disposed in or on the substrate; a conducting pad disposed in the substrate or on the first surface, wherein the conducting pad is electrically connected to the device region; a hole extending from the second surface towards the first surface of the substrate; a wiring layer disposed on the second surface of the substrate and extending towards the first surface of the substrate along a sidewall of the hole to make electrical contact with the conducting pad, wherein a thickness of a first portion of the wiring layer located directly on the conducting pad is smaller than a thickness of the second portion of the wiring layer located directly on the sidewall of the hole; and an insulating layer disposed between the substrate and the wiring layer.