Patents by Inventor Yuan-Sung Chang

Yuan-Sung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating semiconductor device
    Patent number: 9153665
    Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 6, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-An Yu, Yuan-Sung Chang, Yi-Fong Lin, Chin-Piao Chang, Chih-Huang Wu, Wen-Chieh Wang
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20140252459
    Abstract: Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chien-An Yu, Yuan-Sung Chang, Yi-Fong Lin, Chin-Piao Chang, Chih-Huang Wu, Wen-Chieh Wang
  • Semiconductor structure and fabrication method thereof
    Patent number: 8536635
    Abstract: A semiconductor structure includes a semiconductor substrate having thereon a plurality of deep trenches and a plurality of pillar structures between the deep trenches, wherein each of the plurality of pillar structures comprises an upper portion and a lower portion. A doping region is formed in the lower portion. A diffusion barrier layer is disposed on a sidewall of the lower portion.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: September 17, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Chien-An Yu, Yuan-Sung Chang, Feng-Ling Chen, Chun-Hung Chien