Patents by Inventor Yuan Tan

Yuan Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12260633
    Abstract: A defect detection method includes obtaining a first image corresponding to a first area on an object revealing an apparent defect, the first area bounding the area showing the apparent defect; selecting a detection model according to a size of the first image, the detection model selected being one of a group of three models based on dimensions of image, the image being in one of portrait, landscape, or regular square proportions; detecting and confirming or denying a defect on the first image according to the detection model and outputting a detection result, the use of only three possible AI models reduces the likelihood of mis-determinations. An electronic device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 25, 2025
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Fu-Yuan Tan, Ching-Han Cheng
  • Publication number: 20230414668
    Abstract: The present application relates to the prevention or treatment of symptoms and diseases caused by viral infections, such as acute respiratory distress syndrome (ARDS), sepsis or septic shock associated with SARS-CoV-2 and influenza virus infections. The treatment is based on the use of mesenchymal stem cells (MSCs) genetically engineered to overexpress suitable polypeptides such as angiopoeitin-1 (ANGPT1) and IFN-induced transmembrane (IFITM). The MSC-based therapy may be administered to the lung of the patient by injection into the blood system.
    Type: Application
    Filed: October 15, 2021
    Publication date: December 28, 2023
    Inventors: Shirley H.J. MEI, Luciana DE SOUZA MOREIRA, Yuan TAN, Yan WANG
  • Publication number: 20230196756
    Abstract: A defect detection method includes obtaining a first image corresponding to a first area on an object revealing an apparent defect, the first area bounding the area showing the apparent defect; selecting a detection model according to a size of the first image, the detection model selected being one of a group of three models based on dimensions of image, the image being in one of portrait, landscape, or regular square proportions; detecting and confirming or denying a defect on the first image according to the detection model and outputting a detection result, the use of only three possible AI models reduces the likelihood of mis-determinations. An electronic device and a non-volatile storage medium therein, for performing the above-described method, are also disclosed.
    Type: Application
    Filed: May 24, 2022
    Publication date: June 22, 2023
    Inventors: FU-YUAN TAN, CHING-HAN CHENG
  • Publication number: 20220383158
    Abstract: A method for classifying failures can determine consumer devices on-line as being repairable or not to be repaired. The method obtains a training set, the set including information as to total failure and information as to repairable failure. First key information in repairable failure and second key information in total failure are obtained. A first TF-IDF value of each first key information and a second TF-IDF value of each second key information are computed. A first feature bank is created based on the first TF-IDF value and a first threshold value, and a second feature bank is created based on the second TF-IDF value and a second threshold. Target failure is classified by the trained classifier. A failure classification is quickly achieved. An electronic device and a computer readable storage medium applying the method are also provided.
    Type: Application
    Filed: November 18, 2021
    Publication date: December 1, 2022
    Inventors: FU-YUAN TAN, CHING-HAN CHENG
  • Patent number: 11286592
    Abstract: The present invention discloses a method for producing unidirectional hybrid-braided fabrics, including: preparing a first layer of 0° warps; preparing a second layer of 0° warps to a Nth layer of 0° warps; preparing an auxiliary layer of wefts; preparing binding yarns; laying and hybrid-braiding the materials prepared in steps 1-4 to obtain unidirectional hybrid-braided fabrics; and cutting and winding. The 0° warps and wefts of the invention are made of two or more layers of different fibers that are laid in a single direction and finally hybrid-braided. Therefore, two or more different types of materials can be laid, thereby ensuring the uniform distribution and thickness of the fibers in different areas of the hybrid-braided fabric. The grammage of different 0° warp fiber layers can be adjusted freely in a range of 30-3000 grams/m2, thereby realizing performance and cost designability of a composite material.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 29, 2022
    Assignee: NEWTRY COMPOSITE CO., LTD.
    Inventors: Yuan Tan, Xiangwei Chen, Zhiqiang Wang, Bo Geng, Qing Niu, Liewei Zhu
  • Patent number: 10110204
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 23, 2018
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 10103717
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 16, 2018
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9921593
    Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: March 20, 2018
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Publication number: 20180054191
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 22, 2018
    Inventors: James Lawrence GORECKI, Han-Yuan TAN
  • Publication number: 20180010270
    Abstract: The present invention discloses a method for producing unidirectional hybrid-braided fabrics, including: preparing a first layer of 0° warps; preparing a second layer of 0° warps to a Nth layer of 0° warps; preparing an auxiliary layer of wefts; preparing binding yarns; laying and hybrid-braiding the materials prepared in steps 1-4 to obtain unidirectional hybrid-braided fabrics; and cutting and winding. The 0° warps and wefts of the invention are made of two or more layers of different fibers that are laid in a single direction and finally hybrid-braided. Therefore, two or more different types of materials can be laid, thereby ensuring the uniform distribution and thickness of the fibers in different areas of the hybrid-braided fabric. The grammage of different 0° warp fiber layers can be adjusted freely in a range of 30-3000 grams/m2, thereby realizing performance and cost designability of a composite material.
    Type: Application
    Filed: June 18, 2015
    Publication date: January 11, 2018
    Applicant: NEWTRY COMPOSITE CO., LTD.
    Inventors: Yuan TAN, Xiangwei CHEN, Zhiqiang WANG, Bo GENG, Qing NIU, Liewei ZHU
  • Patent number: 9837998
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 5, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Publication number: 20170207864
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
    Type: Application
    Filed: March 31, 2017
    Publication date: July 20, 2017
    Inventors: James Lawrence GORECKI, Han-Yuan TAN
  • Patent number: 9647643
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 9, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Publication number: 20170126217
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Application
    Filed: December 9, 2016
    Publication date: May 4, 2017
    Inventors: James Lawrence GORECKI, Han-Yuan TAN
  • Publication number: 20170126329
    Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.
    Type: Application
    Filed: December 9, 2016
    Publication date: May 4, 2017
    Inventors: James Lawrence GORECKI, Han-Yuan TAN
  • Patent number: 9552006
    Abstract: The present disclosure provides a detailed description of techniques for implementing a wideband low dropout voltage regulator with power supply rejection boost. More specifically, some embodiments of the present disclosure are directed to a voltage regulator comprising a voltage regulator core powered by a supply voltage and providing a regulated voltage output, and a power supply feed forward injection module delivering an injection signal to the voltage regulator core to effect a power supply rejection of the supply voltage variation from the regulated voltage. In one or more embodiments, the injection signal is determined from the supply voltage variation and a gain factor that is based on various design attributes of the output stage of the voltage regulator core. In one or more embodiments, the power supply feed forward injection module comprises a supply voltage sense circuit, a low pass filter, and one or more selectable transconductance amplifiers.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 24, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9553569
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 24, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Publication number: 20160352372
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
    Type: Application
    Filed: August 8, 2016
    Publication date: December 1, 2016
    Inventors: James Lawrence GORECKI, Han-Yuan TAN
  • Patent number: 9432000
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: August 30, 2016
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9042970
    Abstract: A system for facilitating remote medical diagnosis and consultation of heart disease for a patient, the system comprising: a diagnostic device for performing Electrocardiography on the patient, a network device in communication with the diagnostic device via wired or wireless communication links, a software program pre-installed in the network device, a server located remotely, wherein during operation, the patient activates the diagnostic device which will perform Electrocardiography on the patient, the diagnostic device receives diagnostic data and transmits the diagnostic data to the network device, the software program transmit the diagnostic data to over a network to a server which a physician have access to, and based on the diagnostic data gathered by the server and some additional medical data, the physician can review the patient's health condition and offer an appropriate feedback and diagnosis for the patient.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: May 26, 2015
    Inventors: Ying-Chiang Lu, Kae Yuan Tan, Saravanan Sundaramoorthy, Lanzi Jiang, Xiong Kai Teo