Patents by Inventor Yuan-Te Hou

Yuan-Te Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12131109
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Patent number: 12008302
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang, Yung-Chin Hou
  • Publication number: 20240086613
    Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Te Hou, Min-Yuan Tsai
  • Publication number: 20240086610
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Yen-Hung LIN, Yuan-Te HOU, Chung-Hsing WANG
  • Patent number: 11861288
    Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, the slanted layout component having a side slanted from a base axis is detected. In one aspect, an offset angle of the side of the slanted layout component with respect to the base axis is determined. In one aspect, the slanted layout component is rotated according to the offset angle to obtain a rotated layout component. The rotated layout component may have a rotated side in parallel with or perpendicular to the base axis. In one aspect, layout verification can be performed on the rotated layout component with respect to the base axis.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Te Hou, Min-Yuan Tsai
  • Patent number: 11853678
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Publication number: 20230306181
    Abstract: A method performed by a computer system includes: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device; determining leakage probabilities according to the cell abutment cases; calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values; and generating a layout of the semiconductor device according to the expected boundary leakages. Two of the leakage probabilities correspond to two of the cell abutment cases, respectively, and the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
  • Publication number: 20230253477
    Abstract: A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.
    Type: Application
    Filed: May 20, 2022
    Publication date: August 10, 2023
    Inventors: Sheng-Hsiung Wang, Chun-Yen Lin, Yen-Hung Lin, Yuan-Te Hou, Tung-Heng Hsieh
  • Patent number: 11720738
    Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Patent number: 11714949
    Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Publication number: 20230205966
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung CHANG, Yuan-Te HOU, Chung-Hsing WANG, Yung-Chin HOU
  • Publication number: 20230153507
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Patent number: 11593546
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung Chang, Yuan-Te Hou, Chung-Hsing Wang, Yung-Chin Hou
  • Publication number: 20230045023
    Abstract: Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, the slanted layout component having a side slanted from a base axis is detected. In one aspect, an offset angle of the side of the slanted layout component with respect to the base axis is determined. In one aspect, the slanted layout component is rotated according to the offset angle to obtain a rotated layout component. The rotated layout component may have a rotated side in parallel with or perpendicular to the base axis. In one aspect, layout verification can be performed on the rotated layout component with respect to the base axis.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yuan-Te Hou, Min-Yuan Tsai
  • Patent number: 11574106
    Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 11574108
    Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Yuan-Te Hou, Chung-Hsing Wang
  • Patent number: 11294286
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai, Ken-Hsien Hsieh, Shih-Ming Chang, Yuan-Te Hou
  • Publication number: 20210390240
    Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuang-Hung CHANG, Yuan-Te HOU, Chung-Hsing WANG, Yung-Chin HOU
  • Patent number: 11182527
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 11176303
    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou