Patents by Inventor Yuan-Ting Chuang

Yuan-Ting Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249649
    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 11, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Publication number: 20250063776
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.
    Type: Application
    Filed: September 27, 2023
    Publication date: February 20, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
  • Publication number: 20240162220
    Abstract: A capacitor on a fin structure includes a fin structure. A dielectric layer covers the fin structure. A first electrode extension is embedded within the fin structure. A first electrode penetrates the dielectric layer and contacts the first electrode extension. A second electrode and a capacitor dielectric layer are disposed within the dielectric layer. The capacitor dielectric layer surrounds the second electrode, and the capacitor dielectric layer is between the second electrode and the first electrode extension.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
  • Publication number: 20210210628
    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Patent number: 10991824
    Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Publication number: 20200203523
    Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.
    Type: Application
    Filed: January 21, 2019
    Publication date: June 25, 2020
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Patent number: 10528997
    Abstract: A system includes an online shopping platform, a ingredient database assembly and a control unit. The control unit transmits to the online shopping platform entries of active ingredient data and preservative ingredient data respectively corresponding to an active ingredient and a preservative ingredient and respectively stored in an active ingredient database and a preservative ingredient database of the ingredient database assembly, for allowing selection of at least one of the entries via the online shopping platform to result in a desired formula. The desired formula is used for subsequent production of a customized ingredient composition when it is determined that the desired formula conforms with rules of formulation.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 7, 2020
    Assignee: DRSIGNAL BIOTECHNOLOGY CO., LTD.
    Inventors: Hsin-Wu Mi, Yuan-Ting Chuang, Ming-Cheng Lee, Ting-Chieh Lin, Yi-Hao Huang
  • Publication number: 20180240175
    Abstract: A system includes an online shopping platform, a ingredient database assembly and a control unit. The control unit transmits to the online shopping platform entries of active ingredient data and preservative ingredient data respectively corresponding to an active ingredient and a preservative ingredient and respectively stored in an active ingredient database and a preservative ingredient database of the ingredient database assembly, for allowing selection of at least one of the entries via the online shopping platform to result in a desired formula. The desired formula is used for subsequent production of a customized ingredient composition when it is determined that the desired formula conforms with rules of formulation.
    Type: Application
    Filed: November 10, 2017
    Publication date: August 23, 2018
    Inventors: Hsin-Wu MI, Yuan-Ting CHUANG, Ming-Cheng LEE, Ting-Chieh LIN, Yi-Hao HUANG
  • Publication number: 20170222026
    Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 3, 2017
    Inventors: Yi-Ren Chen, Shou-Wei Hsieh, Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Che-Hung Liu