Abstract: This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.

Abstract: A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Abstract: Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

Abstract: An automatic auto-sensing flood protection roller shutter with auto-locating reinforced column includes a door plate composed of a plurality of door panels, at least one reinforced column automatically movable by a motor to a reinforcing position behind the door plate when the door plate is lowered upon sensing a flood, and a bolt and bolt driving device for securing the at least one reinforced column in the reinforcing position.

Abstract: A method for preventing or treating immunoinflammatory dermal disorders is provided.

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: An intelligent electric grid management system and method includes at least one feeder line controller, which is arranged between a secondary power transforming station and at least one power supply feeder line to receive high voltage power and a control instruction from the secondary power transforming station and to store and set, in advance, digital code data of each power supply feeder line, a smart meter of a user end, appliance loads, and priority cutoff levels, a plurality of smart meters, which are each connected between the distribution line of each user end and at least one power feeder line, wherein the smart meter and the feeder line controller transmit therebetween a user end load ON/OFF control signal and a load state detection feedback signal through the power supply feeder line by means of the power line communication protocol; and a plurality of intelligent load receptacles, which are connected to the receptacle power line of the distribution line of the user end and the household appliance l

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Abstract: A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.