Patents by Inventor Yuan Wei

Yuan Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271236
    Abstract: This application provides a rotation mechanism, a supporting apparatus, and a foldable screen terminal, and relates to the field of electronic device technologies, so as to balance a lifting stroke of the lifting member and a thickness of the foldable screen terminal in an unfolded state. The rotation mechanism includes a lifting member, a shaft cover, a first swing arm, a second swing arm, a forcing structure, and a first supporting member. The lifting member includes a lamination surface. The shaft cover is located on a side that is of the lifting member and that is away from the lamination surface. The first swing arm and the second swing arm are respectively located on two opposite sides of the lifting member, and the first swing arm and the second swing arm can swing between an unfolded position and a folded position relative to the shaft cover.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: April 8, 2025
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Lei Feng, Yameng Wei, Haifei Li, Yangjie Tang, Yuan Wang
  • Patent number: 12268756
    Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 8, 2025
    Assignee: MegaPro Biomedical Co. Ltd.
    Inventors: Wen-Yuan Hsieh, Yuan-Hung Hsu, Chia-Wen Huang, Ming-Cheng Wei, Chih-Lung Chen, Shian-Jy Wang
  • Patent number: 12270846
    Abstract: A measuring system and a measuring method of an antenna pattern based on near field to far field transformation (NFTF) are provided. The measuring system includes a probe antenna, a reference antenna, and a control system. The probe antenna measures an electric field radiated by an antenna under test to obtain electric field information. The reference antenna measures the electric field to obtain a reference phase. The control system is coupled to the antenna under test, the probe antenna, and the reference antenna, wherein the control system applies near field focusing to the reference antenna to configure a focus point of the reference antenna on the antenna under test, and the control system performs the NFTF according to the electric field information and the reference phase to output far field patterns.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 8, 2025
    Assignee: Chunghwa Telecom Co., Ltd.
    Inventors: Chang-Lun Liao, You-Hua Lin, Jiahn-Wei Lin, Bo-Cheng You, Chang-Fa Yang, De-Xian Song, Wen-Jiao Liao, Yuan-Chang Hou, Tswen-Jiann Huang
  • Patent number: 12256352
    Abstract: A method and an apparatus for obtaining timing advance value. The method comprises: receiving (S101) a time domain signal, which contains at least part of a reference signal; extracting (SI 02), from the time domain signal, a first group of signal parts including at least one signal part, and a second group of signal parts including at least one signal part, wherein the first group of signal parts do not overlap the second group of signal parts; and determining (S103) a timing advance, TA, value based on an energy of a signal part in the first group of signal parts and an energy of a signal part in the second group of signal parts, wherein the energy of the signal part is based on correlation between the signal part and the reference signal. Therefore, the TA value may be obtained based on a time domain signal.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: March 18, 2025
    Assignee: Teleonaktiebolaget LM Ericsson (Publ)
    Inventors: Dongsheng Sang, Ruiping Wei, Wenwen Liu, Yuan Wang, Wenling Bai
  • Patent number: 12253509
    Abstract: A multiphase flow cylindrical model test system includes a loading structure, a multiphase flow displacement model bucket, a data acquisition and analysis system, a flexible seepage model bucket and a dynamic control system. A multi-parameter test method in the displacement process of pollutants in three-dimensional multi-field and multiphase media is reasonably configured based on the sequential and superimposed application requirements of heat and steam in the thermal enhanced soil vapor extraction process.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: March 18, 2025
    Assignee: INSTITUTE OF ROCK AND SOIL MECHANICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Qiang Xue, Zhixiang Chen, Yong Wan, Mingli Wei, Jiangshan Li, Lei Liu, Yijun Chen, Yuan Li
  • Patent number: 12252555
    Abstract: A selenium-chelating pea oligopeptide, a preparation method thereof and use thereof. After the selenium-chelating pea oligopeptide is subjected to digestion treatment in at least one of following three ways, a change rate of selenium content not more than 3% with respect to the selenium content before the digestion treatment: hydrolyzing for 4 hours by a pepsin at a pH value of 2 and a temperature of 37° C.; hydrolyzing for 6 hours by a trypsin at a pH value of 7.5 and a temperature of 37° C.; maintaining the temperature constant at 37° C., firstly hydrolyzing for 4 hours by the pepsin at a pH value of 2, and then continuing to hydrolyze for 6 hours by a trypsin at a pH value of 6.8. The preparation method thereof includes mixing and reacting an aqueous solution of pea oligopeptide and sodium selenite, and then being subjected to alcohol precipitation and drying.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 18, 2025
    Assignee: CHINA NATIONAL RESEARCH INSTITUTE OF FOOD & FERMENTATION INDUSTRIES CO., LTD.
    Inventors: Muyi Cai, Ruizeng Gu, Jun Lu, Wenying Liu, Xiuyuan Qin, Xingchang Pan, Zhe Dong, Yong Ma, Yaguang Xu, Yongqing Ma, Liang Chen, Lu Lu, Haixin Zhang, Ying Wei, Yan Liu, Kelu Cao, Jing Wang, Guoming Li, Ming Zhou, Yuchen Wang, Yuqing Wang, Kong Ling, Yuan Bi, Xinyue Cui
  • Patent number: 12249539
    Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
  • Patent number: 12250826
    Abstract: An integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The memory cell is over the substrate. The memory cell includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element. The magnetic shielding element is around the memory cell. The interlayer dielectric layer surrounds the memory cell and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Jen Lee, Harry-Hak-Lay Chuang, Tien-Wei Chiang, Hung Cho Wang, Kuei-Hung Shen, Sheng-Huang Huang
  • Patent number: 12249649
    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 11, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Publication number: 20250081508
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.
    Type: Application
    Filed: January 19, 2024
    Publication date: March 6, 2025
    Inventors: Yuan Tsung TSAI, Yao Jui KUO, Chia-Wei FAN, Ying Ming WANG, Shih-Hao CHEN, Ling-Sung WANG
  • Patent number: 12243901
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 4, 2025
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 12234145
    Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.
    Type: Grant
    Filed: November 18, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Wei Chang, Ya-Jen Sheuh, Ren-Dou Lee, Yi-Chih Chang, Yi-Hsun Chiu, Yuan-Hsin Chi
  • Patent number: 12233692
    Abstract: The invention refers to a light-transmissive plastic plate structure suitable for vehicle sunroof with curved surface and a method for fabricating the same. By using polymer material formulation, UV resistant coating formulation and precision coating technology, the wear resistance of polymer surface of plastic substrate can be improved to the same level as glass, and the original optical and physical properties after various environmental tests can also be maintained. The plastic substrate is first formed into a curved plastic plate through a hot pressing process, and then a connecting structure is formed and fixed on the plastic plate by an insert-molding injection process, in order to replace the traditional car sunroof mechanism which is assembled by glass plate bonded with metal connecting parts.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: February 25, 2025
    Assignee: Enflex Corporation
    Inventors: Hsin Yuan Chen, Jui Lin Hsu, Lung Hsiang Peng, Teng Hsiang Wei, Yong-Xin Chen, Zong Yang Li
  • Publication number: 20250063776
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.
    Type: Application
    Filed: September 27, 2023
    Publication date: February 20, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Chun-Hao Lin, Yuan-Ting Chuang, Shou-Wei Hsieh
  • Patent number: 12220734
    Abstract: An information handling system stylus self-cleans a magnet garage arrangement with a garage variable magnet having a first magnetic attraction when the stylus is proximate and information handling system garage and a second magnetic attraction when the stylus is distal the information handling system garage. The second magnetic attraction has a reduced attractive force at the stylus housing outer surface to discourage attraction of contaminants that might scratch or otherwise damage the housing.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: February 11, 2025
    Assignee: Dell Products L.P.
    Inventors: Kuan-Hung Chou, Yuan-Wei Chang, David W. Grunow, Yi-Chung Chu, Chin-Chung Wu, Ai-Wei Liu
  • Patent number: 12224824
    Abstract: Embodiments of this application disclose an antenna power control method and an electronic device. The specific solution is: obtaining, by a first sensor, statuses of at least two detection channels, where each of the detection channels corresponds to one status, the status is any one of a first state and a second state, the first state indicates that a value of capacitance between an antenna corresponding to the detection channel and a human body is greater than a first threshold, and the second state indicates that the value of the capacitance between the antenna corresponding to the detection channel and the human body is less than the first threshold; determining, by a first driving module, a first range value based on the statuses of the at least two detection channels; and controlling, by the processor, transmit power of the at least two antennas based on the first range value.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: February 11, 2025
    Assignee: Honor Device Co., Ltd..
    Inventors: Yuan Xu, Hang Meng, Kunpeng Wei, Shaojie Chu
  • Publication number: 20250048645
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi-Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 12208365
    Abstract: A gene chip includes a chip carrier, a plurality of DNA nanoballs assembled on the chip carrier, and a polymer film formed on the chip carrier and wrapping the DNA nanoballs. The polymer film includes at least one of a film of a positively charged polymer, a film of a positively charged polymer which is modified, a film of a zwitterionic polymer, and a composite polymer film. The composite polymer film is formed by a layer-by-layer self-assembly process of a positively charged polymer and a negatively charged polymer. The gene chip has good sequencing quality and different functions can be achieved by coating with different polymers, such as the chip surface rapidly drying out and surface non-specific adsorption. A method of preparing a gene chip is further disclosed.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: January 28, 2025
    Assignee: BGI SHENZHEN
    Inventors: Zhao-Hui Wang, Hui Wang, Cheng-Mei Xing, Han-Dong Li, Wen-Wei Zhang, Jay Willis Shafto, Mei-Hua Gong, Jin Yang, Yin-Ling Luo, Zhen-Hua Zhang, Yuan Li, Xue-Qin Jiang
  • Publication number: 20250029940
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 23, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
  • Patent number: D1062727
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: February 18, 2025
    Assignee: Dell Products L.P.
    Inventors: Tzu-Wei Tai, Toshiyuki Tanaka, Chao Long Chou, Yuan-Ping Chu, Derric Christopher Hobbs, Michael Ellis Smith