Patents by Inventor Yuan Wen Lin

Yuan Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods for forming metal layers in openings and apparatus for forming same
    Patent number: 10153203
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin
  • Methods for Forming Metal Layers in Openings and Apparatus for Forming Same
    Publication number: 20180151429
    Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.
    Type: Application
    Filed: August 1, 2017
    Publication date: May 31, 2018
    Inventors: Yu-Sheng Wang, Yu-Ting Lin, Hung-Chang Hsu, Hsiao-Ping Liu, Hung Pin Lu, Yuan Wen Lin