Patents by Inventor Yuan Xie

Yuan Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176845
    Abstract: Methods and devices, the method including receiving a matrix of a neural network model; classifying at least a portion of the matrix as a first section based on a first distribution pattern of non-zero elements of the portion of the matrix; and identifying memory addresses of the non-zero elements in the first section of the matrix for loading, according to a first order determined based on the first distribution pattern, the non-zero elements in the first section into one or more vector registers.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Guoyang CHEN, Yu PU, Yongzhi ZHANG, Weifeng ZHANG, Yuan XIE
  • Publication number: 20240161245
    Abstract: In an image optimization method, an image generation network, a to-be-optimized image, and a plurality of preset image features are obtained. A target feature is selected from the plurality of preset image features based on (i) the target feature and the to-be-optimized image and (ii) a preset similarity condition. The target feature and an initial offset parameter are input to the image generation network. The initial offset parameter is adjusted according to a difference between an output of the image generation network and the to-be-optimized image, to obtain a target offset parameter. The target feature and the target offset parameter are input to the image generation network, to generate an optimized image. Apparatus and non-transitory computer-readable storage medium counterpart embodiments are also contemplated.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Chuming LIN, Yanbo WANG, Donghao LUO, Ying TAI, Zhizhong ZHANG, Yuan XIE, Chengjie WANG
  • Publication number: 20240160933
    Abstract: Methods and apparatus for reducing a size of a neural network model, the method including: compressing data of the neural network model; identifying structure information of a vector register, wherein the structure information includes a number of registers included in the vector register; comparing a number of elements in the compressed data with a first condition, wherein the first condition is determined based on the number of registers in the vector register; and in response to the number of elements satisfying the first condition, associating the compressed data with the vector register to enable loading the compressed data to the vector register.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Weifeng ZHANG, Guoyang CHEN, Yu PU, Yongzhi ZHANG, Yuan XIE
  • Patent number: 11947821
    Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for managing a primary storage unit of an accelerator. The methods include assessing activity of the accelerator; assigning, based on the assessed activity of the accelerator, a lease to a group of one or more pages of data on the primary storage unit, wherein the assigned lease indicates a lease duration; and marking, in response to the expiration of the lease duration indicated by the lease, the group of one or more pages of data as an eviction candidate.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 2, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Yongbin Gu, Pengcheng Li, Tao Zhang, Yuan Xie
  • Patent number: 11921814
    Abstract: Methods and devices, the method including receiving a matrix of a neural network model; classifying at least a portion of the matrix as a first section based on a first distribution pattern of non-zero elements of the portion of the matrix; and identifying memory addresses of the non-zero elements in the first section of the matrix for loading, according to a first order determined based on the first distribution pattern, the non-zero elements in the first section into one or more vector registers.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Guoyang Chen, Yu Pu, Yongzhi Zhang, Weifeng Zhang, Yuan Xie
  • Patent number: 11915138
    Abstract: Methods and apparatus for reducing a size of a neural network model, the method including: compressing data of the neural network model; identifying structure information of a vector register, wherein the structure information includes a number of registers included in the vector register; comparing a number of elements in the compressed data with a first condition, wherein the first condition is determined based on the number of registers in the vector register; and in response to the number of elements satisfying the first condition, associating the compressed data with the vector register to enable loading the compressed data to the vector register.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 27, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Weifeng Zhang, Guoyang Chen, Yu Pu, Yongzhi Zhang, Yuan Xie
  • Patent number: 11900239
    Abstract: Systems and methods for dynamically executing sparse neural networks are provided. In one implementation, a system for providing dynamic sparsity in a neural network may include at least one memory storing instructions and at least one processor configured to execute the instructions to: reduce an input vector and a set of weights of the neural network, execute an input layer of the neural network using the reduced input vector and set of weights to generate a reduced output vector; expand the reduced output vector to a full output vector using first predictable output neurons (PONs); using a PON map, reduce a dimension of the full output vector; execute subsequent layers of the neural network using the reduced full output vector to produce a second reduced output vector; and expand the second reduced output vector to a second full output vector using second PONs.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 13, 2024
    Assignee: Alibaba Group Holding Limited
    Inventors: Zhenyu Gu, Liu Liu, Shuangchen Li, Yuan Xie
  • Publication number: 20230394300
    Abstract: This application describes methods, systems, and apparatus, for neural network-based program sampling (NPS). An example device may obtain an assembly code of a program and an execution trace of the program, and divide the assembly code into a plurality of execution intervals. The device may construct a plurality of code graphs respectively corresponding to the plurality of execution intervals, and for each of the plurality of code graphs: generate a plurality of graph snapshots based on the code graph and the execution trace of the program; embed, by using a Graph Neural Network, the plurality of graph snapshots into a plurality of vectors; and aggregate the plurality of vectors into an execution embedding. The device may cluster the plurality of execution embeddings into a plurality of clusters and select representative execution intervals of the program based on the plurality of clusters for execution.
    Type: Application
    Filed: October 28, 2022
    Publication date: December 7, 2023
    Inventors: Yuanwei FANG, Jian CHEN, Yen-Kuang CHEN, Yuan XIE
  • Patent number: 11816574
    Abstract: An input weight pattern of a machine learning model may be received. The input weight pattern may be pruned to produce an output weight pattern based on a predetermined pruning algorithm. The pruning algorithm may include partitioning the input weight pattern into a plurality of sub-patterns, each row of the input weight pattern including sub-rows of a first number of sub-patterns, and each column of the input weight pattern including sub-columns of a second number of sub-patterns; and pruning sub-columns and sub-rows from the plurality of sub-patterns to achieve predetermined column and row sparsities respectively, with a constraint that at least one sub-row in each row of the input weight pattern is not pruned. The output weight pattern may further be compressed to produce a compact weight pattern. The compact weight pattern has lower memory and computational overheads as compared to the input weight pattern for the machine learning model.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 14, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Ao Ren, Yuhao Wang, Tao Zhang, Yuan Xie
  • Patent number: 11755903
    Abstract: The present disclosure relates to systems and methods for providing block-wise sparsity in neural networks. In one implementation, a system for providing block-wise sparsity in a neural network may include at least one memory storing instructions and at least one processor configured to execute the instructions to: divide a matrix of weights associated with a neural network into a plurality of blocks; extract non-zero elements from one or more of the plurality of blocks; re-encode the extracted non-zero elements as vectors with associated coordinates of the extracted non-zero elements within the one or more blocks; enforce input sparsity in the neural network corresponding to the associated coordinates; and execute the neural network using the vectors and the enforced input sparsity.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 12, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Maohua Zhu, Zhenyu Gu, Yuan Xie
  • Patent number: 11657065
    Abstract: Systems and methods include causing presentation of a first cluster in association with an event of the first cluster, the first cluster from a first set of clusters of events. Each event includes a time stamp and event data. Based on the presentation of the first cluster, an extraction rule corresponding to the event of the first cluster is received from a user. Similarities in the event data between the events are determined based on the received extraction rule. The events are grouped into a second set of clusters based on the determined similarities. Presentation is caused of a second cluster in association with an event of the second cluster, where the second cluster is from the second set of clusters.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: May 23, 2023
    Assignee: Splunk Inc.
    Inventors: Jesse Brandau Miller, Katherine Kyle Feeney, Yuan Xie, Steve Zhang, Adam Jamison Oliner, Jindrich Dinga, Jacob Leverich
  • Patent number: 11651012
    Abstract: A method includes in response to a user selection of a command of a coding language, causing display of a set of argument blocks in a text input region based on syntax of the command Each argument block allows the user to input a value of an argument of the command to the argument block. In response to a user selection to modify the set of argument blocks, an argument block is added to the set of argument blocks displayed in the text input region based on the syntax of the command. In response to receiving from the user the input of the value of the argument to the added argument block, the command is caused to be coded in the text input region with at least the argument having the value from the input to the added argument block.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Splunk Inc.
    Inventors: Jindrich Dinga, Yuan Xie, Katherine Kyle Feeney, Jesse Miller
  • Publication number: 20230142598
    Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
    Type: Application
    Filed: September 22, 2022
    Publication date: May 11, 2023
    Inventors: Yi XU, Nuwan S. JAYASENA, Yuan XIE
  • Patent number: 11625341
    Abstract: The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 11, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Jilan Lin, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie
  • Publication number: 20230047378
    Abstract: In various embodiments, this application provides an audio information processing method, an audio information processing apparatus, an electronic device, and a storage medium. An audio information processing method in an embodiment includes: obtaining a first audio feature corresponding to audio information; performing, based on an audio feature at a specified moment in the first audio feature and audio features adjacent to the audio feature at the specified moment, an encoding on the audio feature at the specified moment to obtain a second audio feature corresponding to the audio information; obtaining decoded text information corresponding to the audio information; and obtaining, based on the second audio features and the decoded text information, text information corresponding to the audio information.
    Type: Application
    Filed: January 8, 2021
    Publication date: February 16, 2023
    Inventors: Jilan LIN, Dimin NIU, Shuangchen LI, Hongzhong ZHENG, Yuan XIE
  • Patent number: 11474703
    Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 18, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi Xu, Nuwan S. Jayasena, Yuan Xie
  • Publication number: 20220300577
    Abstract: Methods and devices, the method including receiving a matrix of a neural network model; classifying at least a portion of the matrix as a first section based on a first distribution pattern of non-zero elements of the portion of the matrix; and identifying memory addresses of the non-zero elements in the first section of the matrix for loading, according to a first order determined based on the first distribution pattern, the non-zero elements in the first section into one or more vector registers.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 22, 2022
    Inventors: Guoyang CHEN, Yu PU, Yongzhi ZHANG, Weifeng ZHANG, Yuan XIE
  • Patent number: 11409684
    Abstract: A processing element/unit can include a plurality of networks, a plurality of cores, crossbar interconnects, a plurality of memory controllers and local memory on an integrated circuit (IC) chip. The plurality of cores can be coupled together by the plurality of networks on chip. The crossbar interconnects can couple the networks of cores to the plurality of memory controllers. The plurality of memory controllers can be configured to access data stored in off-chip memory. The local memory can be configured to cache portions of the accessed data. The local memory can be directly accessible by the network of processing cores, or can be distributed across the plurality of memory controllers. The memory controllers can be narrow channel (NC) memory controllers having widths of 4, 8, 12, 16 or a multiple of 4 bits.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 9, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Jilan Lin, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie
  • Patent number: 11403783
    Abstract: A system for processing encoded image components for artificial intelligence tasks. The system can include one or more compute units, one or more controllers and memory. The one or more controllers can include one or more micro-op schedulers and one or more channel switches. The one or more compute units can be configured to process components of the transformed domain image data according to one or more micro-operations for an artificial intelligence task. The one or more channel switches can be configured to selectively control the transfer of the components of transformed domain image data to the one or more compute units based on one or more gating flags. The one or more channel switches can also be configured to selectively control generation of the one or more micro-operations by the one or more micro-op schedulers based on the one or more gating flags.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 2, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Kai Xu, Minghai Qin, Yuhao Wang, Fei Sun, Yen-kuang Chen, Yuan Xie
  • Patent number: 11366875
    Abstract: Methods and devices, the method including receiving a matrix of a neural network model; classifying at least a portion of the matrix as a first section based on a first distribution pattern of non-zero elements of the portion of the matrix; and identifying memory addresses of the non-zero elements in the first section of the matrix for loading, according to a first order determined based on the first distribution pattern, the non-zero elements in the first section into one or more vector registers.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 21, 2022
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Guoyang Chen, Yu Pu, Yongzhi Zhang, Weifeng Zhang, Yuan Xie