Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.

Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: Methods and apparatus are provided for detecting a syncMark in a read channel, such as a hard disk drive. A syncMark is detected in a sector in an iterative read channel by obtaining a sector signal from a storage media, the sector signal comprising a first syncMark, data and a second syncMark substantially at an end of the sector; determining whether the first syncMark is detected in the sector signal; searching for the second syncMark if the first syncMark is not detected in the sector signal; and detecting and decoding the sector signal based on a detection of the second syncMark. The second syncMark may be positioned, for example, following data in the sector signal. The second syncMark can be searched for in a window within the signal sector that is based on an estimated location of the first syncMark.

Abstract: Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a Na×Nw data pattern. The Na×Nw data pattern includes Na bits repeated Nw times. Both Na and Nw are each greater than one. The methods further include performing an initial read of the Na×Nw data pattern, which is stored to a first register.

Abstract: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

Abstract: Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.

Abstract: Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide methods for modifying magnetic information transfer. The methods include retrieving magnetically represented data from a storage medium, and converting the magnetically represented data to a series of data samples. A preceding pattern and a transition status is identified in the series of data samples, and an equalized channel response is computed based on an estimated NLTS value. An error value is computed that corresponds to a difference between the estimated NLTS value and an actual NLTS value, and a pre-compensation value is computed based at least in part on the error value.

Abstract: In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.

Abstract: Greater error protection is provided to error-prone bits that are generated from irregular soft-decoded error correction codes. Error protection is increased to error-prone bits that of interest in a particular system (e.g., parity check bits). One or more extra bits are added to each codeword in the encoding process. The one or more extra bits correspond to lower weights. The one or more extra bits are discarded after each codeword is decoded.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes at least a first detector, a second detector, a decoder, and a queuing buffer. The first detector is operable to perform a data detection on an input data set at a first time. The decoder receives a derivation of an output from the first detector and performs a decoding process. Where the decoding process fails to converge, the decoder output is passed to the second detector for a subsequent detection and decoding process at a second time.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.

Abstract: Embodiments of the present invention provide optimization of read/write channels in a recording system by embedding channel optimization algorithm/procedure into the channels, or a system-on-chip (SOC) where a read/write channel is integrated with a disk drive controller, according to an Embedded Channel Optimization Solution (ECOS).

Abstract: Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.

Abstract: Various embodiments of the present invention provide systems and methods for using channel bit density estimates to adjust fly-height. For example, various embodiments of the present invention provide methods for adaptively adjusting fly-height. Such methods include providing a storage medium that includes information corresponding to a process data set, and a read/write head assembly that is disposed a variable distance from the storage medium. The process data set is accessed from the storage medium. A first channel bit density estimate is adaptively calculated based at least in part on the process data set and a second channel bit density estimate that was previously calculated. The variable distance is modified based at least in part on the first channel bit density estimate. A third channel bit density is adaptively calculated based at least in part on the process data set and a fourth channel bit density estimate that was previously calculated.

Abstract: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint.

Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.

Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.