Abstract: A navigation system for a motor vehicle is provided. A display interface is located in a vehicle. A is processor in communication with a vehicle sensor and a server. The processor is configured to receive vehicle information and road information, predict a traveling direction of the vehicle based on the vehicle information, and highlight the road information associated with the traveling direction on the display interface. A corresponding vehicle and method is also provided. A user of a navigation map can obtain auxiliary information to drive on the current route from a navigation interface more conveniently during the process of using the navigation map, thus providing the user an improved driving experience.

Abstract: A display panel and method of manufacturing the same are provided. The method of manufacturing the display panel includes the steps of providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming a polysilicon layer on the gate insulating layer, performing a first gray-scale mask process on the polysilicon layer to form a source region, a drain region and an active region located between the source region and the drain region by the polysilicon layer, forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer, forming a first electrode layer on the interlayer dielectric layer, performing a second gray-scale mask process on the first electrode layer and the interlayer dielectric layer.

Abstract: An array substrate, a manufacturing method of the array substrate, and a display device are provided. A first metal layer of the array substrate includes first gate lines arranged in parallel and spaced relationship. A second metal layer includes data lines arranged in parallel and spaced relationship and at least one second gate line spaced from the data lines. The first gate lines are vertical to the data lines and intersect them. Each second gate line is above a corresponding one of the first gate lines. Each via hole set of the insulating layer is arranged corresponding to each second gate line. Each via hole set includes at least two via holes spaced from each other. Each second gate line contacts the first gate line under it via a corresponding via hole set.

Abstract: A system for delivering power and data over a single wire via a hub, wherein the hub can control and power multiple low-power Class 2 circuits. The hub can be controlled remotely through a computing device such as a mobile phone or a computer.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: A manufacturing method of an array substrate and the array substrate are provided. The method comprises: forming an active layer on a substrate; forming an insulation layer on the active layer; forming a first metal layer on the insulation layer; forming an interlayer dielectric layer and a pixel electrode layer on the first metal layer by a same mask; forming a second metal layer on the interlayer dielectric layer, wherein the second metal layer comprises a source electrode, a drain electrode, and a touch signal line; and forming a patterned protective layer and a patterned common electrode layer on the second metal layer.

Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Abstract: A polarization grating having a light-shielding layer and a manufacturing method for the same are disclosed. The method includes steps of: forming a metal layer on a substrate, forming a shielding layer on the metal layer, wherein the shielding layer includes a light-shielding pattern layer and a polarization grating pattern layer and etching the metal layer 20 according to the shielding layer to form a polarization grating, wherein the polarization grating includes a polarization section and a light-shielding section directly connected to the polarization section. The present invention improves the compactness of the display panel.

Abstract: A manufacturing method of an array substrate and the array substrate are provided. The method comprises: forming an active layer on a substrate; forming an insulation layer on the active layer; forming a first metal layer on the insulation layer; forming an interlayer dielectric layer and a pixel electrode layer on the first metal layer by a same mask; forming a second metal layer on the interlayer dielectric layer, wherein the second metal layer comprises a source electrode, a drain electrode, and a touch signal line; and forming a patterned protective layer and a patterned common electrode layer on the second metal layer.

Abstract: A manufacturing method of a display panel is provided and includes providing a substrate; and forming a buffer layer, a polysilicon layer, a gate electrode, an interlayer insulating layer, a first transparent electrode layer, a source electrode and drain electrode line, and a touch control line on the substrate in sequence. A masking process is omitted using a planarization layer as a photoresist layer of the interlayer insulating layer. One more masking process is omitted by forming the pixel electrode, the source electrode and drain electrode line and the touch control line in a same masking process.

Abstract: A display panel and a display device are provided, which the display panel including a display substrate, a counter substrate, and a backlight. The display substrate includes a first thin film transistor layer, a touch electrode, and a pixel definition layer. The substrate includes a second thin film transistor layer and a photosensitive component. The second thin film transistor layer has a plurality of thin film transistors. The photosensitive component is connected to an underside of the second thin film transistor layer. The photosensitive component receives a reflected light of a user's fingerprint to identify an identification of the user.

Abstract: An array substrate and a manufacturing method thereof in the embodiment of the present invention can complete the process of the array substrate with the touch function by using six photolithography processes, thereby simplifying the production process, saving cost, and shortening the production cycle.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel comprises a glass substrate, an insulating layer, a polysilicon layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain contacting layer, wherein the polysilicon layer is defined with a first doped region, a second doped region, and a third doped region. The source-drain contacting layer contacts the first doped region and the third doped region. A doping type of the first doped region and a doping type of the third doped region are different so that the first doped region and the third doped region form a PN structure. Doping type of the first doped region and a doping type of the second doped region are same.

Abstract: A manufacturing method of a display panel is provided and includes providing a substrate; and forming a buffer layer, a polysilicon layer, a gate electrode, an interlayer insulating layer, a first transparent electrode layer, a source electrode and drain electrode line, and a touch control line on the substrate in sequence. A masking process is omitted using a planarization layer as a photoresist layer of the interlayer insulating layer. One more masking process is omitted by forming the pixel electrode, the source electrode and drain electrode line and the touch control line in a same masking process.

Abstract: A method of solving a stress based on force boundary and balance condition, the method including: 1) measuring a macro-geometric feature of a research object, and establishing a geometric feature description equation corresponding to the macro-geometric feature; 2) analyzing a specific gravity distribution feature of the research object, and establishing a specific gravity distribution equation of the research object in a research area; 3) analyzing a feature of boundary condition stress of the research object, and establishing a boundary condition stress equation corresponding to the feature of boundary condition stress; 4) selecting a stress expression equation satisfying corresponding balance equation and a boundary condition equation of a force; and 5) analyzing a stress feature of the research object in detail according to an existing strength criterion; and performing comparative analysis on a deformation feature of the research object, and determining a behavior feature of the research object.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.