Patents by Inventor Yuan-Yu Chung

Yuan-Yu Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055361
    Abstract: A method for forming alignment keys of a semiconductor structure includes: forming an oxide pad layer and a passivation layer on a substrate; forming a patterned photoresist layer on the passivation layer, and using the patterned photoresist layer as a mask to remove part of the oxide pad layer and passivation layer and expose the substrate surface in the medium voltage and alignment mark regions; forming oxide portions on the exposed substrate surface, and the oxide portions extending into the first depth of the substrate; forming deep doped wells in the low voltage and medium voltage regions; thinning the oxide portions; forming high-voltage doped wells in the high voltage and alignment mark regions; performing an etching process on the high voltage and alignment mark regions to form a second trench, as an alignment key, having a second depth greater than the first depth in the alignment mark region.
    Type: Application
    Filed: September 26, 2022
    Publication date: February 15, 2024
    Inventors: TSUNG-YU YANG, Shin-Hung Li, Shan-shi Huang, Ruei Jhe Tsao, Che-Hua Chang, YUAN YU CHUNG
  • Publication number: 20240006525
    Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Yuan Yu Chung, Bo-Yu Chen, You-Jia Chang, Lung-En Kuo, Kun-Yuan Liao, Chun-Lung Chen
  • Publication number: 20230346304
    Abstract: The present invention provides a method for OSA (Obstructive Sleep Apnea) severity detection using recording-based electrocardiography (ECG) Signal. The major feature of the present invention emphasizes on using a recording-based ECG Signal as an input, which is different from the deep learning-based prior art of using segment-based signals as an input to a model, and the segment-based signals has only two classification results, i.e. normal or apnea. The present invention provides a method for a model to detect and output directly a value of apnea-hypopnea index (AHI) for the OSA Severity.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Sin Horng Chen, Cheng Yu Yeh, Chun Cheng Lin, Shaw Hwa Hwang, Yuan Fu Liao, Yih Ru Wang, Kuan Chun Hsu, You Shuo Chen, Yao Hsing Chung, Yen Chun Huang, Chi Jung Huang, Li Te Shen, Bing Chih Yao, Ning Yun Ku
  • Publication number: 20230346302
    Abstract: The present invention provides a method for OSA (Obstructive Sleep Apnea) severity classification by using recording-based Peripheral Oxygen Saturation Signal. The major feature of the present invention emphasizes on using a recording-based Peripheral Oxygen Saturation Signal (SpO2 signal) as an input, which is different from the deep learning-based prior art of using segment-based signals as an input to a model, and the segment-based signals has only two classification results, i.e. normal or apnea.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Sin Horng Chen, Cheng Yu Yeh, Chun Cheng Lin, Shaw Hwa Hwang, Yuan Fu Liao, Yih Ru Wang, Kai Yang Qiu, You Shuo Chen, Yao Hsing Chung, Yen Chun Huang, Chi Jung Huang, Li Te Shen, Bing Chih Yao, Ning Yun Ku
  • Patent number: 11735185
    Abstract: The present invention provides a caption service system for remote speech recognition, which provides caption service for the hearing impaired. This system includes a speaker and a live broadcast equipment at A, a listener-typist and a computer at B, a hearing impaired and a live screen at C, and an automatic speech recognition (ASR) caption server at D. Connect the live broadcast equipment, the computer, the live screen and the ASR caption server with a network. The speaker's audio is sent to the automatic speech recognition (ASR) caption server to be converted into text, which is corrected by the listener-typist, and then the text caption is sent to the live screen of the hearing impaired together with the speaker's video and audio, so that the hearing impaired can see the text caption spoken by the speaker.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: August 22, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Sin Horng Chen, Yuan Fu Liao, Yih Ru Wang, Shaw Hwa Hwang, Bing Chih Yao, Cheng Yu Yeh, You Shuo Chen, Yao Hsing Chung, Yen Chun Huang, Chi Jung Huang, Li Te Shen, Ning Yun Ku
  • Publication number: 20230253356
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 10, 2023
    Inventors: Shan-Yu HUANG, Ming-Da CHENG, Hsiao-Wen CHUNG, Ching-Wen HSIAO, Li-Chun HUNG, Yuan-Yao CHANG, Meng-Hsiu HSIEH
  • Patent number: 11688708
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shan-Yu Huang, Ming-Da Cheng, Hsiao-Wen Chung, Ching-Wen Hsiao, Li-Chun Hung, Yuan-Yao Chang, Meng-Hsiu Hsieh
  • Patent number: 10892194
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200328126
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10741455
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200176331
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10607897
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Publication number: 20200035568
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 30, 2020
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng
  • Patent number: 10475709
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Ching-Ling Lin, Po-Jen Chuang, Yu-Ren Wang, Wen-An Liang, Chia-Ming Kuo, Guan-Wei Huang, Yuan-Yu Chung, I-Ming Tseng