Abstract: A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.

Abstract: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.