Abstract: Embodiments of a lead frame for a packaged semiconductor device are provided, one embodiment including: a die pad; a first row of active lead fingers that are laterally separated from one another along their entire length; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein the package body perimeter is located laterally around the die pad; a first dummy lead finger positioned in parallel next to an initial active lead finger of the first row of active lead fingers, wherein the first dummy lead finger and the initial active lead finger are laterally separated from one another along their entire length, and wherein the first dummy lead finger is separated from the package body perimeter by a gap distance; and a first tie bar connected to an outside edge of the first dummy lead finger.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: A lead frame based semiconductor die package includes a lead frame having a die pad that supports a semiconductor die and lead fingers that surround the die and die pad. The die is electrically connected to the lead fingers with bond wires. The die and bond wires are covered with an encapsulant with ends of the lead fingers projecting out from the encapsulant. One set of the lead fingers are bent and project down and another set of the lead fingers are bent and project inwardly, and under a bottom surface of the encapsulant. The encapsulant includes a slot or groove for receiving the lead fingers of the second set.

Abstract: A lead frame based semiconductor die package includes a lead frame having a die pad that supports a semiconductor die and lead fingers that surround the die and die pad. The die is electrically connected to the lead fingers with bond wires. The die and bond wires are covered with an encapsulant with ends of the lead fingers projecting out from the encapsulant. One set of the lead fingers are bent and project down and another set of the lead fingers are bent and project inwardly, and under a bottom surface of the encapsulant. The encapsulant includes a slot or groove for receiving the lead fingers of the second set.

Abstract: A method of assembling a semiconductor device includes providing a lead frame having a die pad and a fame member with lead fingers that surround the die pad. The lead fingers have distal ends connected to the frame member and proximal ends near the die pad. A die is attached to the die pad and die connection pads are electrically connected to the proximal ends of the lead fingers with bond wires. The die, bond wires, and part of the lead fingers are encapsulated with an encapsulant. The encapsulating process includes separating the lead fingers into first and second sets of lead fingers. The proximal ends of the first set lie in a first plane and the proximal ends of the second set lie in a second plane that is spaced and maintained from the first plane solely by the encapsulation material.

Abstract: A lead frame (10) for a quad flat non-leaded semiconductor package (606), includes a tie bar (12), a first group of leads (22) extending a first length from the tie bar (12) in a transverse direction (Y), and a second group of leads (24) extending a second length from the tie bar (12) in the transverse direction (Y). The second length is greater than the first length, and leads from the first and second group of leads (22, 24) alternate in a longitudinal direction (X) along the tie bar (12) so that the first and second groups of leads are staggered. The second group of leads (24) is displaced from the first group of leads (22) in a Z-direction (Z) perpendicular to both the transverse (Y) and longitudinal (X) directions. The leads of the first and second groups of leads (22, 24) each have a respective contact terminal (26 and 28) at their distal ends. The contact terminals (26 and 28) each have a contact face (40 and 42) in a contact plane (44).