Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link state management system includes an upstream device, a downstream device and a link. The upstream device outputs a configuration request to the downstream device to change a device power state of the downstream device. At the time, the link is in a first link state. The downstream device outputs a power entering signal to the upstream device and counts a time period. The link enters to a recovery state and further then return to the first link state if the downstream device does not receive a power request acknowledging signal before the time period is expired.

Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link power state management system includes an upstream device, a downstream device and a link. First, the upstream device outputs a configuration request to the downstream device so as to change a device power state of the downstream device. At the time, the link is in a first link state. Next, the downstream device outputs a power entering signal to the upstream device. Following that, the upstream device outputs a power request acknowledging signal to the downstream device in response to the power entering signal and a time period is counting. Finally, the downstream device re-outputs the power entering signal if the link does not enter to an electrical idle state when the time period is expired.

Abstract: In a data buffer space configuration method for requesting data from a target device via a bus, a device count of master device coupled to the bus is detected by the operating system. Then, a first data buffer space is configured to the master device if the device count is not greater than a threshold. On the other hand, a second data buffer space is configured to the master device if the device count is greater than the threshold.

Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link state management system includes an upstream device, a downstream device and a link. The upstream device outputs a configuration request to the downstream device to change a device power state of the downstream device. At the time, the link is in a first link state. The downstream device outputs a power entering signal to the upstream device and counts a time period. The link enters to a recovery state and further then return to the first link state.

Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link power state management system includes an upstream device, a downstream device and a link. First, the upstream device outputs a configuration request to the downstream device so as to change a device power state of the downstream device. At the time, the link is in a first link state. Next, the downstream device outputs a power entering signal to the upstream device. Following that, the upstream device outputs a power request acknowledging signal to the downstream device in response to the power entering signal and a time period is counting. Finally, the downstream device re-outputs the power entering signal if the link does not enter to an electrical idle state when the time period is expired.