Patents by Inventor YUANBO LI

YUANBO LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11643436
    Abstract: The present invention discloses a polypeptide compound, a pharmaceutical composition, and a preparation method and use thereof. The structural formula of the polypeptide compound is shown in general formula (I): Such polypeptide compounds as ?-opioid receptor agonists have the advantages of better activity and the potential to become clinical candidate compounds.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: May 9, 2023
    Assignee: CHENGDU SINTANOVO BIOTECHNOLOGY CO., LTD.
    Inventors: Jian Gao, Xiaoping Fu, Guoqing Zhong, Haibo Zhou, Hai Hu, Xi Hu, Yu Yuan, Yuanbo Li, Sijun Li
  • Patent number: 11448929
    Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 20, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Jinjin Xue, Fang Yan, Xiaowen Si, Lin Hou, Zhixuan Guo, Yuanbo Li, Xiaofang Li
  • Patent number: 11347334
    Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 31, 2022
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Cenhong Duan, Dawei Shi, Fengguo Wang, Feng Li, Hong Liu, Xinguo Wu, Lu Yang, Wentao Wang, Zifeng Wang, Bo Ma, Yuanbo Li, Zhixuan Guo, Jing Zhao, Haiqin Liang
  • Patent number: 11334179
    Abstract: The present disclosure relates to display technology and, particularly, to a display panel and a display device. In the display panel, a bridging connection layer includes multiple bridge electrodes and a touch electrode layer includes multiple first touch electrodes and multiple second touch electrodes. A first electrode unit of each first touch electrodes includes a first electrode subsection. A vertical projection of the first electrode subsection on a plane where the bridging connection layer is located is within a cover of a bridge electrode. In one embodiment, each bridge electrode includes a bridge electrode terminal and a bridge trace, in a second direction where multiple second electrode units of each second touch electrode are arrange, and extension length of the bridge electrode terminal is greater than a width of the bridge trace, and a first corner is formed at a joint of the bridge electrode terminal and the bridge trace.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 17, 2022
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yuanbo Li, Jiachang Gu, Xianbao Song, Tao Peng, Pei He
  • Patent number: 11222908
    Abstract: An array substrate is provided. The array substrate includes a base, a first electrode and a second electrode which are on the base and a touch line on the base, both the first electrode and the second electrode are configured to transmit a display signal, the touch line is configured to transmit a touch signal; the first electrode and the touch line are respectively in different layers, and an orthographic projection of the first electrode on the base at least partially overlaps with an orthographic projection of the touch line on the base. A preparation method of the array substrate and a touch display panel are further provided.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 11, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xinguo Wu, Fengguo Wang, Dawei Shi, Hong Liu, Zifeng Wang, Feng Li, Bo Ma, Zhixuan Guo, Yuanbo Li, Jing Zhao, Cenhong Duan, Haiqin Liang
  • Publication number: 20210373691
    Abstract: A display panel includes a display function layer and a touch function layer. The touch function layer includes a bridging connection layer, an insulating layer and a touch electrode layer. The bridging connection layer includes multiple bridge electrodes. The touch electrode layer includes multiple first touch electrodes and multiple second touch electrodes. The first touch electrode includes multiple first electrode units electrically connected to each other. The second touch electrode includes multiple second electrode units electrically connected to each other. In each of the multiple first touch electrodes, any two adjacent first electrode units are electrically connected through the bridge electrode. The first electrode unit includes a first electrode subsection. A vertical projection of the first electrode subsection on a plane where the bridging connection layer is located is within a coverage of the bridge electrode.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 2, 2021
    Inventors: Yuanbo Li, Jiachang Gu, Xianbao Song, Tao Peng, Pei He
  • Publication number: 20210373689
    Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.
    Type: Application
    Filed: December 4, 2018
    Publication date: December 2, 2021
    Inventors: Cenhong DUAN, Dawei SHI, Fengguo WANG, Feng LI, Hong LIU, Xinguo WU, Lu YANG, Wentao WANG, Zifeng WANG, Bo MA, Yuanbo LI, Zhixuan GUO, Jing ZHAO, Haiqin LIANG
  • Publication number: 20210333608
    Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.
    Type: Application
    Filed: May 16, 2019
    Publication date: October 28, 2021
    Inventors: Lei YAO, Dawei SHI, Wentao WANG, Lu YANG, Haifeng XU, Lei YAN, Jinfeng WANG, Jinjin XUE, Fang YAN, Xiaowen SI, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
  • Publication number: 20210333968
    Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a display area and a peripheral circuit area. The array substrate further includes a plurality of touch electrodes located in the display area; a plurality of touch signal lines connecting the plurality of touch electrodes to the peripheral circuit area; a plurality of first conductor lines extending in a same direction as the plurality of touch signal lines; and a plurality of second conductor lines extending in a different direction from the plurality of touch signal lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: October 28, 2021
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xinguo WU, Fengguo WANG, Dawei SHI, Hong LIU, Zifeng WANG, Feng LI, Bo MA, Zhixuan GUO, Yuanbo LI, Cenhong DUAN, Jing ZHAO
  • Publication number: 20210217894
    Abstract: A CMOS thin film transistor, a method for manufacturing the same, and an array substrate are provided. The method includes: forming a semiconductor layer including an N-type region and a P-type region on a substrate, the N-type region is divided into a first region, a second region, a third region, a fourth region and a fifth region, the P-type region is divided into a sixth region, a seventh region and an eighth region; performing first N-type ion doping on the first region and the fifth region; performing first P-type ion doping on the N-type region; performing second P-type ion doping on the N-type region and the P-type region; performing second N-type ion doping on the first region, the second region, the fourth region, the fifth region, the sixth region and the eighth region; and performing third P-type ion doping on the sixth region and the eighth region.
    Type: Application
    Filed: December 25, 2019
    Publication date: July 15, 2021
    Inventors: Lei YAO, Yezhou FANG, Feng LI, Lei YAN, Jinjin XUE, Chenglong WANG, Yanyan MENG, Jinfeng WANG, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
  • Publication number: 20210139537
    Abstract: The present invention discloses a polypeptide compound, a pharmaceutical composition, and a preparation method and use thereof. The structural formula of the polypeptide compound is shown in general formula (I): Such polypeptide compounds as ?-opioid receptor agonists have the advantages of better activity and the potential to become clinical candidate compounds.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 13, 2021
    Applicant: CHENGDU SINTANOVO BIOTECHNOLOGY CO., LTD.
    Inventors: Jian GAO, Xiaoping FU, Guoqing ZHONG, Haibo ZHOU, Hai HU, Xi HU, Yu YUAN, Yuanbo LI
  • Patent number: 10948604
    Abstract: A high-precision real-time satellite positioning method comprises: establishing a polygonal satellite positioning receiver array comprising a plurality of satellite positioning receiving mechanisms; transmitting, by the satellite positioning receiving mechanisms, and to a processor module, respective IDs and observation coordinates; computing, by the processor module, a physical geometric pattern and an observation geometric pattern; comparing the physical geometric pattern and the observation geometric pattern to extract an offset vector caused by an error, and to generate an offset vector function library; and subtracting the offset vector from an observation value of a phase center of antennas of the satellite positioning receivers to obtain a corrected satellite positioning value.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 16, 2021
    Assignee: BROADGNSS TECHNOLOGIES CO., LTD.
    Inventors: Yan Shen, Yuanbo Li
  • Patent number: 10795228
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 6, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Xiaowen Si, Fang Yan, Jinjin Xue, Lin Hou, Yuanbo Li, Zhixuan Guo, Xiaofang Li
  • Patent number: 10790310
    Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a base substrate, and a metal connecting member, a first insulating layer, a signal line, a second insulating layer and a first electrode which are disposed on the base substrate in this order. The first insulating layer is located between the metal connecting member and the signal line, and the second insulating layer is located between the signal line and the common electrode. A material of the metal connecting member is different from a material of the signal line. The signal line is electrically connected to the first electrode through the metal connecting member. A contact resistance between the material of the metal connecting member and a material of the first electrode is smaller than a contact resistance between the material of the signal line and the material of the first electrode.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 29, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Hong Liu, Xinguo Wu, Fengguo Wang, Dawei Shi, Zifeng Wang, Wentao Wang, Lu Yang, Feng Li, Zhixuan Guo, Yuanbo Li, Bo Ma
  • Publication number: 20200185416
    Abstract: An array substrate is provided. The array substrate include a base, a first electrode and a second electrode which are on the base and a touch line on the base, both the first electrode and the second electrode are configured to transmit a display signal, the touch line is configured to transmit a touch signal; the first electrode and the touch line are respectively in different layers, and an orthographic projection of the first electrode on the base at least partially overlaps with an orthographic projection of the touch line on the base. A preparation method of the array substrate and a touch display panel are further provided.
    Type: Application
    Filed: August 6, 2018
    Publication date: June 11, 2020
    Inventors: Xinguo WU, Fengguo WANG, Dawei SHI, Hong LIU, Zifeng WANG, Feng LI, Bo MA, Zhixuan GUO, Yuanbo LI, Jing ZHAO, Cenhong DUAN, Haiqin LIANG
  • Publication number: 20200176477
    Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a base substrate, and a metal connecting member, a first insulating layer, a signal line, a second insulating layer and a first electrode which are disposed on the base substrate in this order. The first insulating layer is located between the metal connecting member and the signal line, and the second insulating layer is located between the signal line and the common electrode. A material of the metal connecting member is different from a material of the signal line. The signal line is electrically connected to the first electrode through the metal connecting member. A contact resistance between the material of the metal connecting member and a material of the first electrode is smaller than a contact resistance between the material of the signal line and the material of the first electrode.
    Type: Application
    Filed: January 3, 2018
    Publication date: June 4, 2020
    Inventors: Hong Liu, Xinguo Wu, Fengguo Wang, Dawei Shi, Zifeng Wang, Wentao Wang, Lu Yang, Feng Li, Zhixuan Guo, Yuanbo Li, Bo Ma
  • Patent number: 10649568
    Abstract: An array substrate and a method for manufacturing the same, a display panel and a display device are provided. The array substrate includes: a substrate; a gate metal layer arranged on the substrate, the gate metal layer including a gate line and a patterned auxiliary metal; a source and drain metal layer, the source and drain metal layer including source signal lines and touch signal lines, and the source and drain metal layer being separated from the gate metal layer by an insulating layer; a planarization layer arranged on the source and drain metal layer; and a common electrode arranged on the planarization layer. The patterned auxiliary metal is electrically connected to the touch signal lines through first holes penetrating the insulating layer, and is electrically connected to the common electrode through second holes penetrating the insulating layer and third holes penetrating the planarization layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 12, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Xinguo Wu, Fengguo Wang, Dawei Shi, Hong Liu, Feng Li, Zifeng Wang, Bo Ma, Zhixuan Guo, Yuanbo Li, Cenhong Duan, Jing Zhao
  • Patent number: 10634796
    Abstract: The present invention relates to a high-precision real-time satellite positioning apparatus and a method thereof. The present invention has technical features as follows: the apparatus includes a polygonal receiver array formed by a plurality of single-point satellite positioning receivers; an antenna phase center of each single point satellite positioning receiver is disposed at each vertex and center point of the polygonal receiver array; each single-point satellite positioning receiver includes an MCU and a receiver connected with the MCU; and all MCUs are connected in parallel and jointly connected to a processor module.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 28, 2020
    Assignee: BROADGNSS TECHNOLOGIES CO., LTD.
    Inventors: Yan Shen, Yuanbo Li
  • Patent number: 10608089
    Abstract: The present application provides a thin film transistor, an array substrate, a display device and a method of fabricating a thin film transistor. According to embodiments of the present application, the thin film transistor includes: a substrate; a first source/drain electrode on the substrate; an active layer at a side of the first source/drain electrode facing away from the substrate; and a second source/drain electrode at a side of the active layer facing away from the first source/drain electrode. The first source/drain electrode and the second source/drain electrode are electrically connected to the active layer independently.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 31, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Xinguo Wu, Fengguo Wang, Dawei Shi, Hong Liu, Zifeng Wang, Feng Li, Bo Ma, Zhixuan Guo, Yuanbo Li, Cenhong Duan, Jing Zhao
  • Patent number: 10490670
    Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The method includes: forming a first electrode; forming a first insulation layer on the first electrode; forming a first via hole in the first insulation layer; forming an active layer on the first insulation layer, which is electrically connected with the first electrode through the first via hole; forming a gate insulation layer on the active layer; forming a first gate electrode on the gate insulation layer, which overlaps with at least part of the active layer; forming a second insulation layer on the first gate electrode and the gate insulation layer, forming a second via hole in the second insulation layer and the gate insulation layer; forming a pixel electrode on the second insulation layer, which is electrically connected with the active layer through the second via hole.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: November 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Feng Li, Dawei Shi, Fengguo Wang, Hong Liu, Xinguo Wu, Zifeng Wang, Bo Ma, Zhixuan Guo, Yuanbo Li