Patents by Inventor Yuanbo Zhang

Yuanbo Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11232846
    Abstract: The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 25, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yuanbo Zhang, Yajie Bai, Heecheol Kim, Peng Liang, Hailong Wu, Yi Dan
  • Patent number: 10998068
    Abstract: A shift register circuit includes a first circuit, M second circuits, and N third circuits. M and N are both positive integers, N is an integer multiple of M, M is greater than or equal to 2, and a quotient of N and M is greater than or equal to 2. The first circuit includes a first signal output terminal. Each second circuit includes a second signal input terminal connected to the first signal output terminal. Each third circuit includes a third signal input terminal that is connected to one of second signal input terminals of the M second circuits. A second signal output terminal of each second circuit is connected to third signal input terminals of N/M third circuits, and different second signal output terminals are connected to different third signal input terminals.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: May 4, 2021
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhuo Xu, Yuanbo Zhang, Yajie Bai, Haipeng Zhu, Yan Zhou, Hailong Wu, Heecheol Kim, Min Ran
  • Patent number: 10916178
    Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Yajie Bai, Zhuo Xu, Yuanbo Zhang, Yan Fang, Ming Deng, Zijie Tang, Jaikwang Kim
  • Patent number: 10916320
    Abstract: A shift register unit includes a first output control circuit, a first output circuit, a second output control circuit, a second output circuit, a reset circuit, and a node set circuit. The node set circuit is configured to periodically transfer a first voltage having an inactive level to a first node within the shift register unit during being enabled.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 9, 2021
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Chen, Zhi Zhang, Xiuzhu Tang, Yuanbo Zhang, Zhihui Wang, Qian Qian, Lijun Xiong, Tao Zhou, Xing Dong
  • Patent number: 10892028
    Abstract: A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: January 12, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Chongqing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yuanbo Zhang, Xiaolin Wang, Zhuo Xu, Shuai Chen, Zhulin Liu
  • Publication number: 20200286420
    Abstract: A Gate Driver on Array circuit and a driving method thereof, and a display device. The Gate Driver on Array circuit includes at least one group of shift registers, each group of shift registers includes a plurality of shift registers in cascade, the plurality of shift registers including a first shift register, a second shift register connected after the first shift register, and a third shift register connected after the second shift register, wherein the third shift register is provided with an initializing terminal connected to an output terminal of the first shift register.
    Type: Application
    Filed: October 19, 2017
    Publication date: September 10, 2020
    Applicants: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yajie BAI, Zhuo XU, Yuanbo ZHANG, Yan FANG, Ming DENG, Zijie TANG, Jaikwang KIM
  • Publication number: 20200194089
    Abstract: A shift register circuit includes a first circuit, M second circuits, and N third circuits. M and N are both positive integers, N is an integer multiple of M, M is greater than or equal to 2, and a quotient of N and M is greater than or equal to 2. The first circuit includes a first signal output terminal. Each second circuit includes a second signal input terminal connected to the first signal output terminal. Each third circuit includes a third signal input terminal that is connected to one of second signal input terminals of the M second circuits. A second signal output terminal of each second circuit is connected to third signal input terminals of N/M third circuits, and different second signal output terminals are connected to different third signal input terminals.
    Type: Application
    Filed: March 22, 2019
    Publication date: June 18, 2020
    Inventors: Zhuo XU, Yuanbo ZHANG, Yajie BAI, Haipeng ZHU, Yan ZHOU, Hailong WU, Heecheol KIM, Min RAN
  • Publication number: 20200160774
    Abstract: Embodiments of the present disclosure disclose a gate driving circuit, a method for driving the same, and a display apparatus. The gate driving circuit includes N stages of cascaded shift registers, N being an integer greater than or equal to 4. In the N stages of shift registers, an output signal terminal of an nth stage of shift register is connected to an input signal terminal of an (n+l/2)th stage of shift register, and a reset signal terminal of the nth stage of shift register is connected to an output signal terminal of an (n+K)th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N?l/2), K is an integer greater than l/2 and less than l, and l is a number of clock signal lines connected to the gate driving circuit, which is an even number greater than or equal to 4.
    Type: Application
    Filed: August 17, 2018
    Publication date: May 21, 2020
    Inventors: Honggang Gu, Junsheng Chen, Xianjie Shao, Yuanbo Zhang
  • Patent number: 10657879
    Abstract: Embodiments of the present disclosure disclose a gate driving circuit, a method for driving the same, and a display apparatus. The gate driving circuit includes N stages of cascaded shift registers, N being an integer greater than or equal to 4. In the N stages of shift registers, an output signal terminal of an nth stage of shift register is connected to an input signal terminal of an (n+I/2)th stage of shift register, and a reset signal terminal of the nth stage of shift register is connected to an output signal terminal of an (n+K)th stage of shift register, wherein n is an integer greater than or equal to 1 and less than (N?I/2), K is an integer greater than I/2 and less than I, and I is a number of clock signal lines connected to the gate driving circuit, which is an even number greater than or equal to 4.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 19, 2020
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Honggang Gu, Junsheng Chen, Xianjie Shao, Yuanbo Zhang
  • Patent number: 10650769
    Abstract: The present disclosure provides a display substrate such that each pixel unit of the display substrate includes a switching circuit and a control circuit, and the switching circuit is connected to a corresponding gate line, a control circuit of a respective pixel unit, and a corresponding pixel electrode. The control circuit is configured to transmit a data signal on a corresponding data line to a switching circuit of the respective pixel unit under control of a corresponding control signal line, and n is an integer not less than 2. The present disclosure further provides a display device including the above display substrate and a driving method for the above display substrate.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: May 12, 2020
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanbo Zhang, Wenhao You, Rui Xue, Rui Wang, Pengyue Zhang, Xiaolin Wang
  • Publication number: 20200118474
    Abstract: A gate driving circuitry, a method for driving the same and a display device are provided. The gate driving circuitry includes N gate driving units and N groups of clock signal lines, and an n-th gate driving unit is correspondingly connected to an n-th group of clock signal lines, where N is an integer greater than 1, and n is a positive integer less than or equal to N. Each group of clock signal lines includes 2a clock signal lines, where a is equal to 1, or a is an even number; each of the gate driving units includes at least one shift register module; and each shift register module in the n-th gate driving unit is connected to the n-th group of clock signal lines.
    Type: Application
    Filed: July 3, 2018
    Publication date: April 16, 2020
    Applicants: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanbo ZHANG, Shuai CHEN, Rui WANG, Pengcheng FU, Wenlin MEI, Xiaolin WANG, Shouqiang ZHANG
  • Patent number: 10521042
    Abstract: The present disclosure relates to a touch display panel, a method and a device for driving the touch display panel. The method is applied to the touch display panel which includes L gate lines arranged sequentially and M touch scan lines arranged sequentially, where both L and M are positive integers larger than 1. The method includes dividing a duration for which the touch display panel displays each frame of image into N control time intervals with each of the N control time intervals including a display refresh time and a touch time arranged sequentially, where N is an integer larger than 1, during the duration for which the touch display panel displays each frame of image, driving the L gate lines sequentially in N display refresh times, and driving the M touch scan lines sequentially for K times in N touch times, where K is larger than 1.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 31, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianing Lu, Yuanbo Zhang
  • Patent number: 10403228
    Abstract: A shift register unit includes: a discharging TFT, a source electrode and a drain electrode of which are connected to a first low level signal input end and a pull-up node respectively; and a first discharging control unit connected to a gate electrode of the discharging TFT and configured to output a first control signal to the gate electrode of the discharging TFT between a first and a second time points, so as to enable the discharging TFT to be in an on state and output a first low level signal to the pull-up node, thereby to discharge the pull-up node. The first time point is a time point when the processing of a first frame by the shift register is ended, and the second time point is a time point when the processing of a second frame adjacent to the first frame by the shift register is started.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: September 3, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xing Yao, Yuanbo Zhang, Seungwoo Han
  • Patent number: 10388203
    Abstract: The present disclosure provides a GOA unit circuit, a method for driving the same, and a GOA circuit. The GOA unit circuit comprises a first input sub-circuit, a pull-up sub-circuit, a first pull-down sub-circuit, a reset sub-circuit, a second input sub-circuit, a noise control sub-circuit, a first de-noising sub-circuit, and a second de-noising sub-circuit. The first pull-down sub-circuit is connected to an output signal terminal, a first clock control signal terminal and a discharge signal terminal, a discharge signal provided by the discharge signal terminal is at a high level higher than that of an input signal provided by the input signal terminal, and the first pull-down sub-circuit is configured to discharge the output signal terminal under the control of the first clock control signal and the discharge signal, to pull down a potential at the output signal terminal to a low level. The GOA unit circuit is configured to drive gate lines of a display apparatus.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 20, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanbo Zhang, Shuai Chen
  • Publication number: 20190237037
    Abstract: The present disclosure provides a display substrate such that each pixel unit of the display substrate includes a switching circuit and a control circuit, and the switching circuit is connected to a corresponding gate line, a control circuit of a respective pixel unit, and a corresponding pixel electrode. The control circuit is configured to transmit a data signal on a corresponding data line to a switching circuit of the respective pixel unit under control of a corresponding control signal line, and n is an integer not less than 2. The present disclosure further provides a display device including the above display substrate and a driving method for the above display substrate.
    Type: Application
    Filed: January 7, 2019
    Publication date: August 1, 2019
    Inventors: Yuanbo ZHANG, Wenhao YOU, Rui XUE, Rui WANG, Pengyue ZHANG, Xiaolin WANG
  • Publication number: 20190228830
    Abstract: The present disclosure provides a gate drive unit, a driving method thereof and a gate drive circuit. The gate drive unit includes a shift register and a plurality of output control modules. Each of the output control modules is connected to a corresponding clock scanning signal line and a corresponding first scanning signal output terminal, respectively. Each of the output control modules includes a first output control submodule and an output reset submodule. The first output control submodule is connected to a signal output terminal of the shift register, the corresponding clock scanning signal line and the corresponding first scanning signal output terminal, and configured to send a clock scanning signal of the corresponding clock scanning signal line to the corresponding first scanning signal output terminal, under control of a signal outputted by the signal output terminal of the shift register.
    Type: Application
    Filed: November 15, 2018
    Publication date: July 25, 2019
    Inventors: Zhuo XU, Yuanbo ZHANG, Yajie BAI, Heecheol KIM, Peng LIANG, Hailong WU, Yi DAN
  • Publication number: 20190206503
    Abstract: A shift register includes a pull-up control circuit, a pull-up circuit, a pull-down control circuit, a pull-down circuit, and a reset circuit. The pull-down circuit is connected to the pull-down node, the pull-up node, a second control terminal, a first voltage terminal, and a signal output terminal, and is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of the pull-down node; moreover, the pull-down circuit is further configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under the control of a signal from the second control terminal.
    Type: Application
    Filed: August 20, 2018
    Publication date: July 4, 2019
    Inventors: Yuanbo ZHANG, Xiaolin WANG, Zhuo XU, Shuai CHEN, Zhulin LIU
  • Publication number: 20190189234
    Abstract: A shift register unit includes a first output control circuit, a first output circuit, a second output control circuit, a second output circuit, a reset circuit, and a node set circuit. The node set circuit is configured to periodically transfer a first voltage having an inactive level to a first node within the shift register unit during being enabled.
    Type: Application
    Filed: May 30, 2018
    Publication date: June 20, 2019
    Inventors: Shuai CHEN, Zhi ZHANG, Xiuzhu TANG, Yuanbo ZHANG, Zhihui WANG, Qian QIAN, Lijun XIONG, Tao ZHOU, Xing DONG
  • Patent number: 10255985
    Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 9, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mingfu Han, Guangliang Shang, Yuanbo Zhang, Yujie Gao, Yan Yan, Yingmeng Miao, Seungwoo Han, Zhihe Jin, Xing Yao, Haoliang Zheng
  • Patent number: 10217427
    Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: February 26, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuanbo Zhang, Seungwoo Han, Xing Yao