Patents by Inventor Yuancheng Christopher Pan
Yuancheng Christopher Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9634486Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.Type: GrantFiled: July 9, 2014Date of Patent: April 25, 2017Assignee: QUALCOMM INCORPORATEDInventors: Hee Jun Park, Yuancheng Christopher Pan, Christopher Kong Yee Chun
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Patent number: 9620452Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.Type: GrantFiled: November 8, 2016Date of Patent: April 11, 2017Assignee: QUALCOMM INCORPORATEDInventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
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Patent number: 9585242Abstract: A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.Type: GrantFiled: February 20, 2014Date of Patent: February 28, 2017Assignee: QUALCOMM IncorporatedInventors: Ryan Michael Coutts, Yuancheng Christopher Pan
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Publication number: 20170053866Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.Type: ApplicationFiled: November 8, 2016Publication date: February 23, 2017Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN
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Patent number: 9575095Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.Type: GrantFiled: August 13, 2014Date of Patent: February 21, 2017Assignee: QUALCOMM IncorporatedInventors: Junmou Zhang, Chuang Zhang, Yuancheng Christopher Pan, Nan Chen
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Patent number: 9520358Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.Type: GrantFiled: June 19, 2015Date of Patent: December 13, 2016Assignee: QUALCOMM INCORPORATEDInventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
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Publication number: 20160133614Abstract: The present disclosure provides semiconductor packages and methods for fabricating semiconductor packages. The semiconductor package may comprise a semiconductor device mounted to a first substrate, a voltage regulator mounted to the first substrate and coupled to the semiconductor device, and an inductive element located on a perimeter of the semiconductor device and coupled to the voltage regulator, wherein the inductive element is formed by a plurality of interconnected conductive elements extending vertically from the first substrate.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: Shiqun GU, Ratibor RADOJCIC, Mustafa BADAROGLU, Chunlei SHI, Yuancheng Christopher PAN
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Publication number: 20160126180Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.Type: ApplicationFiled: June 19, 2015Publication date: May 5, 2016Inventors: Xiongfei MENG, Joon Hyung CHUNG, Yuancheng Christopher PAN
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Publication number: 20160047847Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.Type: ApplicationFiled: August 13, 2014Publication date: February 18, 2016Inventors: Junmou Zhang, Chuang Zhang, Yuancheng Christopher Pan, Nan Chen
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Publication number: 20160013643Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.Type: ApplicationFiled: July 9, 2014Publication date: January 14, 2016Inventors: Hee Jun Park, Yuancheng Christopher Pan, Christopher Kong Yee Chun
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Publication number: 20150235952Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20150237714Abstract: A package substrate is provided that includes a substrate and a capacitor. The substrate comprises a cavity penetrating a core layer and metal layers of the substrate. The capacitor comprises electrode pads and is disposed in the cavity. One of the metal layers of the substrate includes a discontinuous metal plane, and the electrode pads directly contact the discontinuous metal plane.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: QUALCOMM IncorporatedInventors: Ryan Michael Coutts, Yuancheng Christopher Pan
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Patent number: 9048112Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: GrantFiled: June 29, 2010Date of Patent: June 2, 2015Assignee: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Patent number: 8692368Abstract: A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.Type: GrantFiled: February 7, 2012Date of Patent: April 8, 2014Assignee: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20130285696Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.Type: ApplicationFiled: June 27, 2013Publication date: October 31, 2013Inventors: Lew Chua-Eoan, Boris Andreev, Yuancheng Christopher Pan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
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Publication number: 20120293972Abstract: A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.Type: ApplicationFiled: February 7, 2012Publication date: November 22, 2012Applicant: QUALCOMM INCORPORATEDInventors: Yuancheng Christopher Pan, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20120257618Abstract: A system and method for expanding a chassis network using soft interconnects, including a hybrid chassis comprising a first fabric card comprising a first switching fabric, a second fabric card comprising a second switching fabric, a first set of line cards coupled to the first switching fabric via a first set of hard connections, and coupled to an interface associated with the second switching fabric via a soft connection, and a second set of line cards coupled to the second fabric card.Type: ApplicationFiled: April 5, 2012Publication date: October 11, 2012Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Yuancheng Christopher Pan, Tian Yu, Chongyang Wang, Chunxing Huang, Zhenhua Xu
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Publication number: 20110317387Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20110215863Abstract: A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Applicant: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20110050334Abstract: A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.Type: ApplicationFiled: September 2, 2009Publication date: March 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Yuancheng Christopher Pan, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang