Abstract: In accordance with an embodiment, a direct memory access (DMA) system includes input interface circuitry configured to receive a data packet of a sensor from a source memory. The DMA system comprises processing circuitry configured to determine whether the data packet comprises a synchronized data frame and, when it is determined that the data packet comprises a synchronized data frame, extract a payload of the synchronized data frame. The DMA system comprises output interface circuitry configured to send the payload or data derived from the payload to a destination memory.

Abstract: A novel concept for Near Field Communication (NFC) is described herein. In accordance with the embodiments described herein, orthogonal carrier signals are transmitted between NFC transmitter and NFC receiver circuit. In one arrangement, a carrier signal is unmodulated to ensure uninterrupted energy transfer to the receiver circuit. The orthogonal carriers are used to implement full-duplex Near Field Communication.

Abstract: A novel concept for Near Field Communication (NFC) is described herein. In accordance with the embodiments described herein, orthogonal carrier signals are transmitted between NFC transmitter and NFC receiver circuit. In one arrangement, a carrier signal is unmodulated to ensure uninterrupted energy transfer to the receiver circuit. The orthogonal carriers are used to implement full-duplex Near Field Communication.

Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.

Abstract: An electronic device is described herein. In accordance with one embodiment, the electronic device includes an embedded controller having a debug logic, an interface circuit coupled to the debug logic, and a memory coupled to the interface circuit. The interface circuit is operative to read debug information stored in the debug logic and to transmit the read debug information to the memory. The interface circuit is further operative to receive debug information stored in the memory and write the received debug information into the debug logic.