Patents by Inventor Yuang-Chang Lin

Yuang-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6689673
    Abstract: The proposed invention is related to a method for forming a gate with metal silicide. In short, the proposed method comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a polysilicon layer on the first dielectric layer; forming a metal silicide layer on the polysilicon layer; forming a second dielectric layer on the metal silicide layer; etching the second dielectric layer, the metal silicide layer, the polysilicon layer and the first dielectric layer to form a gate; performing a thermal nitridation process to form a metal nitride layer on the sidewall of the metal silicide layer; and performing a thermal oxidation process to eliminate edge defects.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: February 10, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Kirk Hsu, Yuang-Chang Lin, Wen-Jeng Lin
  • Patent number: 6306760
    Abstract: The present invention relates to a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, an array area and a periphery area. The array area comprises a first gate electrode and a second gate electrode adjacent to the first gate electrode. The periphery area comprises at least a third gate electrode. A first doped area is formed over each of two opposite sides of each gate electrode. A first spacer is formed on a wall of each of the two opposite sides of the third gate electrode in the periphery area. Then, a second spacer is formed on a wall of each of the two opposite sides of the first and second gate electrodes in the array area. The first spacers are thicker than the second spacers, and the second spacers between the first and second gate electrodes are internal walls of a self-aligned contact hole between the first and second gate electrodes.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: October 23, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Tuei Hsu, Yuang-Chang Lin, Wen-Jeng Lin
  • Patent number: 4985661
    Abstract: This invention relates to an interrupted desk lamp generally comprised of a main lamp assembly and an auxiliary lamp assembly. The auxiliary lamp assembly is controlled by means of a photoresistor and an AC power failure lighting circuit to automatically turn on the lamp bulb to provide illumiantion during AC power failure and low intensity of ambient light. The auxiliary lamp assembly may be removed from the device for independent application to serve as an emergency lamp.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: January 15, 1991
    Inventor: Yuang-Chang Lin