Abstract: A conductive wiring layer structure, applied to the conductive wiring layer structure under bonding pads of a die. The die has a substrate and can be partitioned into a central core circuit and a peripheral bonding pad area. The conductive wire layer structure has a plurality of trapezium conductive wiring regions and a plurality of inverse trapezium conductive wiring regions alternately arranged in the bonding pad area. Each of the equilateral and inverse trapezium conductive wiring regions has a plurality of dielectric layers and a plurality of conductive wiring layers alternately overlaying each other on the substrate. The conductive wiring layers of the trapezium conductive wiring region are wider as approaching the substrate, and become narrower as distant away from the substrate. The conductive wiring layers of the inverse trapezium conductive wiring region are narrower as approaching the substrate, and wider as distant away from the substrate.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor signal to determine a particular kind of microprocessors used. According to the microprocessor being using, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various kinds of microprocessors.

Abstract: A conductive wiring layer structure, applied to the conductive wiring layer structure under bonding pads of a die. The die has a substrate and can be partitioned into a central core circuit and a peripheral bonding pad area. The conductive wire layer structure has a plurality of trapezium conductive wiring regions and a plurality of inverse trapezium conductive wiring regions alternately arranged in the bonding pad area. Each of the equilateral and inverse trapezium conductive wiring regions has a plurality of dielectric layers and a plurality of conductive wiring layers alternately overlaying each other on the substrate. The conductive wiring layers of the trapezium conductive wiring region are wider as approaching the substrate, and become narrower as distant away from the substrate. The conductive wiring layers of the inverse trapezium conductive wiring region are narrower as approaching the substrate, and wider as distant away from the substrate.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: A single-end-input voltage level transfer is provided to transfer a first signal into a second signal. The voltage level transfer has a first, a second, a third, and a fourth transistors, a first inverter, and a second inverter, in which the first transistor is an NMOS transistor and the other three are PMOS transistors. A first transistor source is coupled to the first signal. An input end of the first inverter is coupled to a first transistor drain. An output end of the first inverter is coupled to an input end of the second inverter, which exports the second signal. A second transistor source is coupled to a first power source, and a second transistor drain is coupled to a first transistor gate. A second transistor gate is controlled by a complementary second signal. A third transistor source is coupled to a second power source, and a third transistor drain is coupled to the first transistor gate. A third transistor gate is controlled by the second signal.