Abstract: An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect structure is connected to the first bump structure of the first integrated circuit die, and the second conductive structure of the detachable interconnect structure is connected to the second bump structure of the second integrated circuit die. The detachable interconnect structure may also be used to facilitate wafer-level testing prior to packaging the first and second integrated circuit dies to form the integrated circuit package.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

Abstract: An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

Abstract: An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer.

Abstract: An integrated circuit package may include a first integrated circuit die having a first bump structure, a second integrated circuit die having a second bump structure, and a detachable interconnect structure having first and second conductive structures that is positioned between the first and second integrated circuit dies. In order to establish electrical communication between the first and second integrated circuit dies, the first conductive structure of the detachable interconnect structure is connected to the first bump structure of the first integrated circuit die, and the second conductive structure of the detachable interconnect structure is connected to the second bump structure of the second integrated circuit die. The detachable interconnect structure may also be used to facilitate wafer-level testing prior to packaging the first and second integrated circuit dies to form the integrated circuit package.

Abstract: In one embodiment, an integrated circuit package includes a package substrate, a printed circuit board, an interposer structure and a transmission line bridge interconnect within the interposer. The interposer structure, which includes multiple interposer layers, may be formed on a top surface of the package substrate. The printed circuit board may be coupled to the package substrate through the transmission line bridge interconnect. The transmission line may be formed on at least one of the interposer layers. The transmission line may be utilized to convey signals between the package substrate and the printed circuit board. The transmission line may be a stripline transmission line or a micro-strip transmission line. The transmission line may have a low parasitic inductance and implementation of the transmission line does not introduce large dimensional discontinuity throughout that signal pathway. The integrated circuit package may be part of a circuit system that includes external circuits.

Abstract: In a preferred embodiment of the invention, the via comprises one or more stacks, each stack comprising a seed layer of a first electrically conducting material formed on a smooth surface; a trace of a second electrically material that is electroplated on the seed layer; a column in electrical contact with the trace, the column comprising a third electrically conducting material that is electroplated on the trace; and an insulating material on the substrate and trace, the insulating material having a smooth upper surface in which the column is exposed. Additional vias may be stacked in tiers one on top of the other with the seed layer of one via making non-rectifying electrical contact with the exposed column of the via below it. Methods for forming the via structure are also disclosed.

Abstract: An integrated circuit package may include an integrated circuit die with lower and upper surfaces. The integrated circuit die is mounted on a package substrate. An underfill material is deposited between the integrated circuit die and the package substrate. A molding compound may be injected to surround the integrated circuit die while leaving the upper surface of the integrated circuit die exposed. The integrated circuit package further includes a metal layer that contacts the exposed upper surface of the integrated circuit die. The metal layer may also cover the molding compound. If desired, an additional metal layer may be formed on the layer of metal as a heat spreader. Such a configuration may also be applicable for wire bond packages, in which the metal layers are formed on an overmold that is disposed over a wire-bonded integrated circuit die on a package substrate.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

Abstract: A two-dimensional array of bonding pads is formed on a first major surface of a substrate. At least some of the pads are connected to conductors that extend across or into the substrate. The pads can be classified in two groups. A first group is conventional, each pad providing a continuous electrically conductive surface on which a solder ball or solder bump may be formed. In the second group, each pad has a plurality of isolated electrically conductive regions that are connected to different conductors that extend across or into the substrate. Solder balls or solder bumps having a first height are mounted on some of the pads. Multi-terminal devices that have a height that is no more than that of the first height are mounted on at least some of the second group of pads; and their terminals are connected to different electrically conductive regions.

Abstract: A method of forming an integrated circuit package may include forming a first layer of a package substrate and mounting an interposer structure on the first layer of a substrate. In some instances, adhesive is used to attach the interposer structure to the first layer of the substrate. After the interposer structure is mounted on the first layer of the substrate, at least one hole is formed through the interposer structure. The hole may be filled with a conductive material such as copper to form a through-hole via in the interposer structure. A second layer of the substrate may be formed over the interposer structure and the first layer of the substrate. Integrated circuit (IC) dies may be mounted on the substrate and signals may be routed between the IC dies via the interposer structure embedded in the substrate.

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

Abstract: An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.

Abstract: Integrated circuit packages with heat dissipation function are disclosed. A disclosed integrated circuit package includes a first die attached on a top surface of a second die. The second die may be coupled to a thermally conductive block. The thermally conductive block may be embedded in a cavity formed in a package substrate. A heat spreading lid may be disposed over the package substrate. The integrated circuit package may be disposed on a printed circuit substrate via solder bumps or balls. The printed circuit substrate may have heat dissipation paths to dissipate heat from the integrated circuit package.

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

Abstract: The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Abstract: An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.