Patents by Inventor Yuanzhi MA

Yuanzhi MA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081535
    Abstract: Systems, methods and apparatus are provided for transistors having a channel region comprising a crystalline spinel indium-gallium-zinc-oxide (IGZO) material.
    Type: Application
    Filed: July 25, 2024
    Publication date: March 6, 2025
    Inventors: Adharsh Rajagopal, Scott E. Sills, Yi Fang Lee, Glen H. Walters, Alexandre Marc Subirats, Yuanzhi Ma
  • Publication number: 20250056828
    Abstract: Some implementations herein provide for a memory device and methods of formation. The memory device includes a plurality of storage cells arranged vertically and a plurality of corresponding gate all around transistors. Methods of forming the memory device include using a single trench to remove a liner material and form recesses that define cell contact lightly-doped drain regions of the gate all around transistors. Using the single trench to remove the liner material and form the recesses that define the cell contact lightly-doped drain region widths causes the cell contact lightly-doped drain regions to be formed having substantially similar widths.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 13, 2025
    Inventors: Si-Woo LEE, Yuichi YOKOYAMA, Scott E. SILLS, Gautham MUTHUSAMY, David HWANG, Yoshitaka NAKAMURA, Pavani Vamsi Krishna NITTALA, Yuanzhi MA, Glen H. WALTERS, Haitao LIU, Kamal M. KARDA
  • Publication number: 20250040121
    Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.
    Type: Application
    Filed: July 18, 2024
    Publication date: January 30, 2025
    Inventors: Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, David K. Hwang, Yoshitaka Nakamura, Yuichi Yokoyama, Pavani Vamsi Krishna Nittala, Glen H. Walters, Gautham Muthusamy, Haitao Liu, Kamal Karda
  • Publication number: 20240098970
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Scott E. Sills, Si-Woo Lee, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20240098969
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: David K. Hwang, Yoshitaka Nakamura, Scott E. Sills, Si-Woo Lee, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20240074141
    Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Yoshitaka Nakamura, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, David K. Hwang
  • Publication number: 20230397391
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 7, 2023
    Inventors: Si-Woo Lee, Scott E. Sills, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
  • Publication number: 20230397390
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 7, 2023
    Inventors: David K. Hwang, John F. Kaeding, Matthew S. Thorum, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, Yoshitaka Nakamura, Glen H. Walters
  • Patent number: 10781815
    Abstract: The present invention discloses a large-flow plunger pump, comprising a box, a crank-link mechanism, a plunger, a suction valve and a discharge valve. On the basis of the conventional multi-cylinder plunger pumps, assemblies such as a detachable upper crosshead guide, an intelligent plunger packing lubrication system, a damping valve, crankshaft support roller assemblies, and a suction-pressure stabilizer having a cooling water coil therein are invented. Both the service life and the reliability of the large-flow plunger pumps are overall improved.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 22, 2020
    Assignee: JINTUO PETROLEUM MICHINERY MANUFACTURING CO., LTD.
    Inventors: Yuanzhi Ma, Qinghe Gao
  • Publication number: 20180135617
    Abstract: The present invention discloses a large-flow plunger pump, comprising a box, a crank-link mechanism, a plunger, a suction valve and a discharge valve. On the basis of the conventional multi-cylinder plunger pumps, assemblies such as a detachable upper crosshead guide, an intelligent plunger packing lubrication system, a damping valve, crankshaft support roller assemblies, and a suction-pressure stabilizer having a cooling water coil therein are invented. Both the service life and the reliability of the large-flow plunger pumps are overall improved.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 17, 2018
    Applicant: JINTUO PETROLEUM MACHINERY MANUFACTRING CO., LTD.
    Inventors: Yuanzhi MA, Qinghe GAO