Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.

Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a source structure in a semiconductor substrate. The semiconductor device structure also includes a channel layer over the semiconductor substrate. A first portion of the channel layer covers a portion of the source structure. A second portion of the channel layer laterally extends away from the source structure. The semiconductor device structure further includes a drain structure over the semiconductor substrate. The drain structure and the source structure have different conductivity types. The drain structure adjoins the second portion of the channel layer.