Patents by Inventor Yu-Chang Chen

Yu-Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009753
    Abstract: A half-bridge flyback power converter: a first transistor, a second transistor and a third transistor which form a half-bridge circuit. The first transistor is turned on for generating a negative circulated current for achieving zero voltage switching of the second transistor. The second transistor is turned on for magnetizing a transformer. The third transistor is turned on during a demagnetized time period to generate an output voltage. The physical size of the first transistor is smaller than physical size of the third transistor.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: June 11, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ta-Yung Yang, Ying-Chieh Su, Yu-Chang Chen
  • Patent number: 11996137
    Abstract: A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-An Chang, Yu-Lin Chen, Chia-Fu Lee
  • Patent number: 11996429
    Abstract: A semiconductor device includes a device layer, a semiconductor layer, a sensor element, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor layer is over the device layer. The semiconductor layer has a plurality of microstructures thereon. Each of the microstructures has a substantially triangular cross-section. The sensor element is under the microstructures of the semiconductor layer and is configured to sense incident light. The dielectric layer is over the microstructures of the semiconductor layer. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.
    Type: Grant
    Filed: November 14, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Nan Tu, Yu-Lung Yeh, Hsing-Chih Lin, Chien-Chang Huang, Shih-Shiung Chen
  • Patent number: 11994809
    Abstract: The present disclosure provides an exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas. The exhaust system includes: a main exhaust pipe positioned above the semiconductor manufacturing equipment and having a top surface and a bottom surface extending parallel to the top surface; a first branch pipe including an upstream end coupled to a source of a gas mixture and a downstream end connected to the main exhaust pipe through the top surface; a second branch pipe including an upstream end and a downstream end connected to the main exhaust pipe through the bottom surface; and a detector configured to detect presence of the hazardous gas in the second branch pipe.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Fu Lin, Shih-Chang Shih, Chia-Chen Chen
  • Patent number: 11988831
    Abstract: A method of displaying a rear-view image and a mobile device using the method are provided. The method includes: receiving the rear-view image; displaying a virtual dashboard through a display; and displaying the rear-view image on a default area of the virtual dashboard in response to receiving a signal associated with a direction indicator light, wherein the default area corresponds to the direction indicator light.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Kinpo Electronics, Inc.
    Inventors: Yu Chi Chen, Hsien Chung Chen, Sheng-Chang Wu
  • Publication number: 20240151932
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: March 28, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
  • Publication number: 20240152029
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
  • Publication number: 20240155234
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: March 27, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
  • Publication number: 20240151935
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
  • Publication number: 20240151936
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: March 27, 2023
    Publication date: May 9, 2024
    Inventors: Hsiao-Hsin HU, Chih-Wen CHIANG, Chia-Che WU, Yu-Chiao LO, Yi-Ho CHEN, Chao-Chang HU, Sin-Jhong SONG
  • Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Patent number: 11962247
    Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ta-Yung Yang, Ying-Chieh Su, Yu-Chang Chen
  • Publication number: 20240120846
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120845
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240113187
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
  • Publication number: 20240071833
    Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Huan Chen, Huan-Chih Yuan, Yu-Chang Jong, Scott Yeh, Fei-Yun Chen, Yi-Hao Chen, Ting-Wei Chou
  • Patent number: 11843321
    Abstract: A control circuit for controlling a power supply circuit to provide power to a system device which includes a communication circuit includes: a pulse width modulation (PWM) controller configured to switch a transformer of the power supply circuit to generate a first output voltage; and a switched capacitor converter configured to generate a second output voltage according to the first output voltage. The second output voltage provides power to the communication circuit, wherein the communication circuit generates a power saving signal to control the PWM controller and the switched capacitor converter. When the power saving signal is enabled, the first output voltage is decreased and a duty ratio of the switched capacitor converter is increased.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: December 12, 2023
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ta-Yung Yang, Wei-Hsu Chang, Yu-Chang Chen, Tsung-Wei Huang, Shui-Mu Lin
  • Patent number: 11776863
    Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: October 3, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi, Sung-Hung Chiang, Yu-Chang Chen
  • Patent number: 11710689
    Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 25, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Yu-Chang Chen