Abstract: A method of fabricating a MOSFET device structure, featuring a double insulator spacer, and improved source and drain engineering, has been developed. A silicon nitride-silicon oxide, double spacer, is used to prevent thinning of the insulator spacer, during a buffered hydrof luoric acid procedure, used prior to a metal deposition and metal silicide formation. A lightly doped source and drain region is formed prior to creation of the silicon oxide spacer, a medium doped source and drain region is formed prior to creation of the silicon nitride spacer, and a heavily doped source and drain region is formed following the creation of the silicon nitride spacer. This source and drain configuration increases device performance and reliability.

Abstract: A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

Abstract: A novel method for improving the etch back uniformity for inter-metal-dielectric planarization was accomplished. Conventional single etch backs use a high polymer chemistry gas mixture (CF.sub.4 /CHF.sub.3) to etch back the planar spin-on-glass (SOG) layer to a conformal insulating barrier layer over a patterned metal. The polymer producing etch gas eliminates micro-loading effects by providing the required selectivity (about 1.6) between the insulating barrier layer and SOG for good planarization, but results in poor etch back uniformity (about 12 to 15%) across the wafer when the SOG is etched. The improved method, of this invention, uses a partial first etch back in a downstream etcher using CF.sub.4 /O.sub.2 having a etch rate that decreases from center to edge of wafer, thereby forming a convex SOG etch rate profile. The remaining SOG layer is then etched to the insulating barrier layer in the CF.sub.4 /CHF.sub.3 etch gas having an etch rate that increases from center to edge of wafer.