Patents by Inventor Yu-Cheng Sun
Yu-Cheng Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088291Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, TsuChing Yang, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11600572Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.Type: GrantFiled: March 11, 2021Date of Patent: March 7, 2023Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich
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Publication number: 20220293526Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich
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Patent number: 11335631Abstract: A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.Type: GrantFiled: August 16, 2020Date of Patent: May 17, 2022Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun, Hung-Chang Kuo, Yung-Yang Liang
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Patent number: 11309936Abstract: A signal transmission device includes a transmission line. The transmission line is configured to receive a signal transmitted from a transmission device, and output the signal to a receiving device. The transmission line includes a signal suppression device. The signal suppression device is coupled to the receiving device, and is configured to suppress a reflection signal reflected from the receiving device. The signal suppression device includes a pull-up element and a compensation element. The pull-up element is configured to decrease an equivalent impedance from the signal suppression device to the receiving device. The compensation element is configured to compensate for the equivalent impedance from the signal suppression device to the receiving device. A first terminal of the pull-up element is coupled to a first terminal of the compensation element, and a second terminal of the compensation element is coupled to the receiving device.Type: GrantFiled: September 22, 2020Date of Patent: April 19, 2022Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Cheng Sun, Sheng-Fan Yang, Yuan-Hung Lin, Yung-Yang Liang
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Publication number: 20210320057Abstract: A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.Type: ApplicationFiled: August 16, 2020Publication date: October 14, 2021Inventors: Sheng-Fan YANG, Yuan-Hung LIN, Yu-Cheng SUN, Hung-Chang KUO, Yung-Yang LIANG
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Publication number: 20210306028Abstract: A signal transmission device includes a transmission line. The transmission line is configured to receive a signal transmitted from a transmission device, and output the signal to a receiving device. The transmission line includes a signal suppression device. The signal suppression device is coupled to the receiving device, and is configured to suppress a reflection signal reflected from the receiving device. The signal suppression device includes a pull-up element and a compensation element. The pull-up element is configured to decrease an equivalent impedance from the signal suppression device to the receiving device. The compensation element is configured to compensate for the equivalent impedance from the signal suppression device to the receiving device. A first terminal of the pull-up element is coupled to a first terminal of the compensation element, and a second terminal of the compensation element is coupled to the receiving device.Type: ApplicationFiled: September 22, 2020Publication date: September 30, 2021Inventors: Yu-Cheng SUN, Sheng-Fan YANG, Yuan-Hung LIN, Yung-Yang LIANG
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Patent number: 10892238Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.Type: GrantFiled: May 16, 2019Date of Patent: January 12, 2021Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Hung Lin, Sheng-Fan Yang, Yu-Cheng Sun
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Patent number: 10790223Abstract: An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.Type: GrantFiled: April 29, 2019Date of Patent: September 29, 2020Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun, Steve S. A. Wan
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Publication number: 20200303330Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.Type: ApplicationFiled: May 16, 2019Publication date: September 24, 2020Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-Hung Lin, Sheng-Fan Yang, Yu-Cheng Sun
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Patent number: 10736209Abstract: A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.Type: GrantFiled: February 15, 2019Date of Patent: August 4, 2020Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun
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Publication number: 20200185313Abstract: An integrated circuit package element provided includes a chip element and a package module coupled to the chip element. The chip element includes two driving units that are electrically connected to each other. The package module includes a grounding area, two individual power distributed networks and a grounded shielding structure which is completely disposed between the individual power distributed networks, electrically connected to the chip element, and configured to block power noise coupling between the first electric power distribution network and the second electric power distribution network. The grounding area is electrically connected to the individual electric power distribution networks and the grounded shielding structure.Type: ApplicationFiled: April 29, 2019Publication date: June 11, 2020Inventors: Sheng-Fan YANG, Yuan-Hung LIN, Yu-Cheng SUN, Steve S.A. WAN
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Publication number: 20200107431Abstract: A conductive transmission line structure includes a first conductive transmission line and a second conductive transmission line. A first segment and a second segment of the first conductive transmission line are respectively disposed adjacent to a third segment and a fourth segment of the second conductive transmission line. Line widths of the first segment and the third segment are respectively smaller than line widths of the second segment and the fourth segment. A spacing between the first segment and the third segment is smaller than a spacing between the second segment and the fourth segment. The first segment and the third segment provide a first impedance, and the second segment and the fourth segment provide a second impedance. The first impedance is smaller than the second impedance. The first and the third signal transmission nodes receive a differential signal pair.Type: ApplicationFiled: February 15, 2019Publication date: April 2, 2020Applicants: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Fan Yang, Yuan-Hung Lin, Yu-Cheng Sun