Patents by Inventor Yu-Chung Wang
Yu-Chung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11995246Abstract: A method for touchless gesture recognition is provided. The method includes transmitting ultrasonic signals via a speaker. The method includes generating ultrasonic signals. The method includes receiving the reflected ultrasonic signals from an object via two or more microphones. The method includes computing a frequency shift according to the reflected ultrasonic signals. The method includes identifying a gesture that corresponds to a movement of the object according to the frequency shift. The method includes performing a function that corresponds to the gesture.Type: GrantFiled: February 13, 2023Date of Patent: May 28, 2024Assignee: FORTEMEDIA, INC.Inventors: Yu-Xuan Xu, Ching-Lung Chan, Shih-Chung Wang, Yen-Son Paul Huang, Shih-Chin Gong
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Publication number: 20240153901Abstract: A first and second semiconductor device are bonded together using a bonding contact pad embedded within a bonding dielectric layer of the first semiconductor device and at least one bonding via embedded within a bonding dielectric layer of the second semiconductor device. The bonding contact pad extends a first dimension in a first direction perpendicular to the major surface of the first semiconductor device and a second dimension in a second direction parallel to the plane of the first semiconductor wafer, the second dimension being at least twice the first dimension. The bonding via extends a third dimension in the first direction and a fourth dimension in the second direction, the third dimension being at least twice the first dimension. The bonding contact pad and bonding via may be at least partially embedded in respective bonding dielectric layers in respective topmost dielectric layers of respective stacked interconnect layers.Type: ApplicationFiled: January 9, 2023Publication date: May 9, 2024Inventors: Yu-Hung Lin, Han-Jong Chia, Wei-Ming Wang, Kuo-Chung Yee, Chen Chen, Shih-Peng Tai
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Publication number: 20240126374Abstract: A method for touchless gesture recognition is provided. The method includes transmitting ultrasonic signals via a speaker. The method includes generating ultrasonic signals. The method includes receiving the reflected ultrasonic signals from an object via two or more microphones. The method includes computing a frequency shift according to the reflected ultrasonic signals. The method includes identifying a gesture that corresponds to a movement of the object according to the frequency shift. The method includes performing a function that corresponds to the gesture.Type: ApplicationFiled: February 13, 2023Publication date: April 18, 2024Inventors: Yu-Xuan XU, Ching-Lung CHAN, Shih-Chung WANG, Yen-Son Paul HUANG, Shih-Chin GONG
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Publication number: 20240128178Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.Type: ApplicationFiled: February 8, 2023Publication date: April 18, 2024Inventors: Yu-Hung LIN, Wei-Ming WANG, Su-Chun YANG, Jih-Churng TWU, Shih-Peng TAI, Kuo-Chung YEE
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Patent number: 11955547Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.Type: GrantFiled: December 20, 2018Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
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Patent number: 11944970Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.Type: GrantFiled: June 10, 2019Date of Patent: April 2, 2024Assignees: INSTANT NANOBIOSENSORS, INC., INSTANT NANOBIOSENSORS CO., LTD.Inventors: Yu-Chung Huang, Yi-Li Sun, Ting-Chou Chang, Jhy-Wen Wu, Nan-Kuang Yao, Lai-Kwan Chau, Shau-Chun Wang, Ying Ting Chen
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Publication number: 20240105664Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.Type: ApplicationFiled: August 16, 2023Publication date: March 28, 2024Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240096830Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Yu-Yi Huang, Yu-Hung Lin, Wei-Ming Wang, Chen Chen, Shih-Peng Tai, Kuo-Chung Yee
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Patent number: 9438179Abstract: An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor. A control terminal of the first transistor receives a reference voltage. A first terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor receives an input voltage. A first terminal of the auxiliary transistor is coupled to a first terminal of the first transistor, a second terminal of the auxiliary transistor is coupled to a second terminal of the first transistor, a control terminal of the auxiliary transistor receives a control voltage, and a base terminal thereof receives a power supply voltage. The current source and load are respectively coupled to the first terminals and second terminals of the first and second transistors.Type: GrantFiled: August 1, 2014Date of Patent: September 6, 2016Assignee: Intel CorporationInventor: Yu-Chung Wang
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Patent number: 9361258Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.Type: GrantFiled: October 21, 2013Date of Patent: June 7, 2016Assignee: RDA TECHNOLOGIES LIMITEDInventors: Feng-Chi Wei, Yu-Chung Wang, Hsiang-Chi Hsieh, Tsan-Hwi Chen
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Patent number: 9331674Abstract: A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first comparator, a second comparator and a logic operation circuit. The signal generator generates a periodic signal. The first comparator receives the periodic signal and respectively compares the periodic signal with a first reference voltage and a second reference voltage to generate a first output signal. The second comparator receives the periodic signal and compares the periodic signal with a first threshold voltage to generate a second output signal. The logic operation circuit performs logic operations on the first output signal and the second output signal so as to generate a plurality of first phase output signals.Type: GrantFiled: August 1, 2014Date of Patent: May 3, 2016Assignee: Intel CorporationInventors: Yu-Chung Wang, Yen-Chin Chen
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Patent number: 9257967Abstract: A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first comparator, a second comparator and a logic operation circuit. The signal generator generates a periodic signal. The first comparator receives the periodic signal and respectively compares the periodic signal with a first reference voltage and a second reference voltage to generate a first output signal. The second comparator receives the periodic signal and compares the periodic signal with a first threshold voltage to generate a second output signal. The logic operation circuit performs logic operations on the first output signal and the second output signal so as to generate a plurality of first phase output signals.Type: GrantFiled: August 1, 2014Date of Patent: February 9, 2016Assignee: INTEL CORPORATIONInventors: Yu-Chung Wang, Yen-Chin Chen
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Publication number: 20150244330Abstract: An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor. A control terminal of the first transistor receives a reference voltage. A first terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor receives an input voltage. A first terminal of the auxiliary transistor is coupled to a first terminal of the first transistor, a second terminal of the auxiliary transistor is coupled to a second terminal of the first transistor, a control terminal of the auxiliary transistor receives a control voltage, and a base terminal thereof receives a power supply voltage. The current source and load are respectively coupled to the first terminals and second terminals of the first and second transistors.Type: ApplicationFiled: August 1, 2014Publication date: August 27, 2015Applicant: VIA TELECOM CO., LTD.Inventor: Yu-Chung Wang
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Publication number: 20150244350Abstract: A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first comparator, a second comparator and a logic operation circuit. The signal generator generates a periodic signal. The first comparator receives the periodic signal and respectively compares the periodic signal with a first reference voltage and a second reference voltage to generate a first output signal. The second comparator receives the periodic signal and compares the periodic signal with a first threshold voltage to generate a second output signal. The logic operation circuit performs logic operations on the first output signal and the second output signal so as to generate a plurality of first phase output signals.Type: ApplicationFiled: August 1, 2014Publication date: August 27, 2015Applicant: VIA Telecom Co., LtdInventors: Yu-Chung Wang, Yen-Chin Chen
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Publication number: 20150113194Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.Type: ApplicationFiled: October 21, 2013Publication date: April 23, 2015Applicant: S2-Tek Inc.Inventors: Feng-Chi Wei, Yu-Chung Wang, Hsiang-Chi Hsieh, Tsan-Hwi Chen
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Publication number: 20090268057Abstract: The present invention is to provide a portable memory device with wireless communication capability which comprises a controller connected with an input/output interface for connecting with a digital photographic device, a first storage unit for saving photographs and photographic information received from the digital photographic device through the input/output interface, a wireless communication module for establishing a wireless transmission path with a wireless communication module of an environmental information recording device and second storage unit for saving environmental information received from the environmental information recording device through the wireless transmission path respectively.Type: ApplicationFiled: April 24, 2008Publication date: October 29, 2009Applicant: Home Scenario Inc.Inventor: Yu-Chung Wang
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Publication number: 20020073129Abstract: An integrated multi-component scheduling process is invented that may emulate various scheduling methods. For general purpose operating systems, the integrated scheduling method can be used to provide more powerful capabilities as many commonly used scheduling methods, including priority-driven, time-driven, and share-driven methods. With a multi-component structure, scheduling policy components can be separated from scheduling mechanism components in an operating system scheduler. The integrated scheduling method can also be used to combine several scheduling policies into one method.Type: ApplicationFiled: December 4, 2000Publication date: June 13, 2002Inventors: Yu-Chung Wang, Kwei-Jay Lin