Abstract: A system for analog computing, an analog computing system with sub-binary radix weight representation is provided. The analog computing system comprises an input node, a multiplexer (MUX), a digital to analog converter (DAC), a SRAM-based Sub-Binary Multiplier (SSBM), an analog to digital converter (ADC), a switch, an output node and a calibration module. The calibration module is configured to control the analog computing system to switch between a calibration mode and a normal operation mode. Prior to being switched to the normal operation mode, the analog computing system is configured to perform a process to calibrate a weight parameter stored in the SSBM. The ADC comprises a plurality of multipliers associated with a plurality of sub-binary weight radixes. The weight parameter stored in the SSBM and the plurality of sub-binary weight radixes are configured to represent a plurality of weights for the analog computing system.

Abstract: A smart antenna system includes: an antenna array including a plurality of antenna elements, and at least one calibration element; a plurality of transceiver units each having a port coupled with an associated one of the antenna elements, a receive port, and a transmit port; a transceiver calibration unit including a port coupled with the calibration element via a coaxial cable, a receive port, and a transmit port; and signal processing means communicatively coupled with each of the receive ports and the transmit ports of each of the transceiver units, and coupled with the calibration receive port and the calibration transmit port of the calibration unit. A transmitter calibration path associated with each antenna element extends from the transmit port of the associated transceiver unit to the associated antenna element, from the associated antenna element to the calibration element, and from the calibration element to the receive port of the calibration unit.

Abstract: A time division duplex switching circuit provides for selectively coupling signals between an antenna and a front stage transceiver circuit. The switching circuit is operative in a transmit mode and in a receive mode, and includes: a transmitter amplifier having an input and an output; a receiver amplifier having an input and an output; a first circulator including a first port coupled for communication with the front stage transceiver, a second port selectively coupled with the output of the receiver amplifier via a first switching, and a third port selectively coupled with the input of the transmitter amplifier via a second switching; and a second circulator including a first port coupled for communication via the antenna, a second port coupled with the input of the receiver amplifier, and a third port coupled with the output of the transmitter amplifier.

Abstract: A wireless communication system has a protocol enabling synchronous code division multiple access (CDMA) communication on a time division duplex (TDD) frequency, and provides for a smart antenna system as an integral component of the system. The protocol has downlink time slots (DTS) which provide for synchronization and paging of all remote terminals from a base station on a omnidirectional code channel and while providing for traffic signals on directional traffic channels. The protocol has uplink time slots (DTS) which enable rapid link requests by remote terminals, as well as enabling improved spacial estimation, synchronization and power control of remote terminals by the base station.